Composition of dependency graphs for asynchronous circuit synthesis based on synchronous circuit scheduling

The results of application of the synchronous circuit scheduling to controlled data flow graph (CDFG) on placing a restriction on the number of usable operators in the circuit are used for specifications in the proposed method for dependency graphs for asynchronous circuit synthesis with the shortest possible execution time. First, in this method, operators are assigned to each operation so that the execution order restriction of the operations by co-use of the operators increases less than it would otherwise. In particular, when conditional branching is involved in the specification, such a branching probability is taken into account. Next, from the binding results, dependency graphs are generated that can be mapped directly to the hardware while the execution sequence restriction of each operation and the conformity of the graphs are taken into account. From the experimental results, it is found that the proposed method functions effectively for the specifications of the actual digital filter and for the hypothetical specifications generated randomly.