Universal test complexity of field-programmable gate arrays

Tomoo Inoue, Hideo Fujiwara, Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

44 Citations (Scopus)

Abstract

A field-programmable gate array (FPGA) can implement arbitrary logic circuits in the field. In this paper, we consider universal test such that when applied to an unprogrammed FPGA, it ensures that all the corresponding programmed logic circuits on the FPGA are fault-free. We focus on testing for look-up tables in FPGAs, and present two types of programming schemes; sequential loading and random access loading. Then we show test procedures for the FPGAs with these programming schemes and their test complexities. In order to make the test complexity for FPGAs independent of the array size of the FPGAs, we propose a programming scheme called block-sliced loading, which makes FPGAs C-testable.

Original languageEnglish
Title of host publicationProceedings of the Asian Test Symposium
PublisherIEEE
Pages259-265
Number of pages7
Publication statusPublished - 1995
Externally publishedYes
EventProceedings of the 1995 4th Asian Test Symposium - Bangalore, India
Duration: Nov 23 1995Nov 24 1995

Other

OtherProceedings of the 1995 4th Asian Test Symposium
CityBangalore, India
Period11/23/9511/24/95

Fingerprint

Field programmable gate arrays (FPGA)
Logic circuits
Testing

ASJC Scopus subject areas

  • Hardware and Architecture
  • Media Technology

Cite this

Inoue, T., Fujiwara, H., Michinishi, H., Yokohira, T., & Okamoto, T. (1995). Universal test complexity of field-programmable gate arrays. In Proceedings of the Asian Test Symposium (pp. 259-265). IEEE.

Universal test complexity of field-programmable gate arrays. / Inoue, Tomoo; Fujiwara, Hideo; Michinishi, Hiroyuki; Yokohira, Tokumi; Okamoto, Takuji.

Proceedings of the Asian Test Symposium. IEEE, 1995. p. 259-265.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Inoue, T, Fujiwara, H, Michinishi, H, Yokohira, T & Okamoto, T 1995, Universal test complexity of field-programmable gate arrays. in Proceedings of the Asian Test Symposium. IEEE, pp. 259-265, Proceedings of the 1995 4th Asian Test Symposium, Bangalore, India, 11/23/95.
Inoue T, Fujiwara H, Michinishi H, Yokohira T, Okamoto T. Universal test complexity of field-programmable gate arrays. In Proceedings of the Asian Test Symposium. IEEE. 1995. p. 259-265
Inoue, Tomoo ; Fujiwara, Hideo ; Michinishi, Hiroyuki ; Yokohira, Tokumi ; Okamoto, Takuji. / Universal test complexity of field-programmable gate arrays. Proceedings of the Asian Test Symposium. IEEE, 1995. pp. 259-265
@inproceedings{a4504fa0570a41cf95c6dd4207a99ac8,
title = "Universal test complexity of field-programmable gate arrays",
abstract = "A field-programmable gate array (FPGA) can implement arbitrary logic circuits in the field. In this paper, we consider universal test such that when applied to an unprogrammed FPGA, it ensures that all the corresponding programmed logic circuits on the FPGA are fault-free. We focus on testing for look-up tables in FPGAs, and present two types of programming schemes; sequential loading and random access loading. Then we show test procedures for the FPGAs with these programming schemes and their test complexities. In order to make the test complexity for FPGAs independent of the array size of the FPGAs, we propose a programming scheme called block-sliced loading, which makes FPGAs C-testable.",
author = "Tomoo Inoue and Hideo Fujiwara and Hiroyuki Michinishi and Tokumi Yokohira and Takuji Okamoto",
year = "1995",
language = "English",
pages = "259--265",
booktitle = "Proceedings of the Asian Test Symposium",
publisher = "IEEE",

}

TY - GEN

T1 - Universal test complexity of field-programmable gate arrays

AU - Inoue, Tomoo

AU - Fujiwara, Hideo

AU - Michinishi, Hiroyuki

AU - Yokohira, Tokumi

AU - Okamoto, Takuji

PY - 1995

Y1 - 1995

N2 - A field-programmable gate array (FPGA) can implement arbitrary logic circuits in the field. In this paper, we consider universal test such that when applied to an unprogrammed FPGA, it ensures that all the corresponding programmed logic circuits on the FPGA are fault-free. We focus on testing for look-up tables in FPGAs, and present two types of programming schemes; sequential loading and random access loading. Then we show test procedures for the FPGAs with these programming schemes and their test complexities. In order to make the test complexity for FPGAs independent of the array size of the FPGAs, we propose a programming scheme called block-sliced loading, which makes FPGAs C-testable.

AB - A field-programmable gate array (FPGA) can implement arbitrary logic circuits in the field. In this paper, we consider universal test such that when applied to an unprogrammed FPGA, it ensures that all the corresponding programmed logic circuits on the FPGA are fault-free. We focus on testing for look-up tables in FPGAs, and present two types of programming schemes; sequential loading and random access loading. Then we show test procedures for the FPGAs with these programming schemes and their test complexities. In order to make the test complexity for FPGAs independent of the array size of the FPGAs, we propose a programming scheme called block-sliced loading, which makes FPGAs C-testable.

UR - http://www.scopus.com/inward/record.url?scp=0029519091&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0029519091&partnerID=8YFLogxK

M3 - Conference contribution

SP - 259

EP - 265

BT - Proceedings of the Asian Test Symposium

PB - IEEE

ER -