Universal test complexity of field-programmable gate arrays

Tomoo Inoue, Hideo Fujiwara, Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto

Research output: Contribution to journalConference article

44 Citations (Scopus)

Abstract

A field-programmable gate array (FPGA) can implement arbitrary logic circuits in the field. In this paper, we consider universal test such that when applied to an unprogrammed FPGA, it ensures that all the corresponding programmed logic circuits on the FPGA are fault-free. We focus on testing for look-up tables in FPGAs, and present two types of programming schemes; sequential loading and random access loading. Then we show test procedures for the FPGAs with these programming schemes and their test complexities. In order to make the test complexity for FPGAs independent of the array size of the FPGAs, we propose a programming scheme called block-sliced loading, which makes FPGAs C-testable.

Original languageEnglish
Pages (from-to)259-265
Number of pages7
JournalProceedings of the Asian Test Symposium
Publication statusPublished - Dec 1 1995
Externally publishedYes
EventProceedings of the 1995 4th Asian Test Symposium - Bangalore, India
Duration: Nov 23 1995Nov 24 1995

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Inoue, T., Fujiwara, H., Michinishi, H., Yokohira, T., & Okamoto, T. (1995). Universal test complexity of field-programmable gate arrays. Proceedings of the Asian Test Symposium, 259-265.