Timing analysis of an optically differential reconfigurable gate array for dynamically reconfigurable processors

Minoru Watanabe; Fuminori Kobayashi

Timing analysis of an optically differential reconfigurable gate array for dynamically reconfigurable processors

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The timing analysis for reconfiguration and the execution of an optical differential reconfigurable gate array (ODRGA) for a dynamically reconfigurable processor was discussed. The reconfigurable timing was analyzed using a 0.35 μm CMOS process ODRGA-VLSI chip. The reconfiguration time of the ODRGA-VLSI chip was separated into three parts which were refresh time, detection time of the optical reconfiguration context, and the response time of differential reconfiguration circuits. It was found that the total time period necessary for optical reconfiguration and subsequent execution of the implementation circuit were 14.4 ns at 69 MHz.

Original language	English
Title of host publication	Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04
Editors	T.P. Plaks
Pages	311
Number of pages	1
Publication status	Published - 2004
Externally published	Yes
Event	Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04 - Las Vegas, NV, United States Duration: Jun 21 2004 → Jun 24 2004

Publication series

Name	Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04

Conference

Conference	Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04
Country/Territory	United States
City	Las Vegas, NV
Period	6/21/04 → 6/24/04

ASJC Scopus subject areas

Engineering(all)

Cite this

Watanabe, M., & Kobayashi, F. (2004). Timing analysis of an optically differential reconfigurable gate array for dynamically reconfigurable processors. In T. P. Plaks (Ed.), Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04 (pp. 311). (Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04).

Timing analysis of an optically differential reconfigurable gate array for dynamically reconfigurable processors. / Watanabe, Minoru; Kobayashi, Fuminori.

Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04. ed. / T.P. Plaks. 2004. p. 311 (Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Watanabe, M & Kobayashi, F 2004, Timing analysis of an optically differential reconfigurable gate array for dynamically reconfigurable processors. in TP Plaks (ed.), Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04. Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04, pp. 311, Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04, Las Vegas, NV, United States, 6/21/04.

Watanabe M, Kobayashi F. Timing analysis of an optically differential reconfigurable gate array for dynamically reconfigurable processors. In Plaks TP, editor, Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04. 2004. p. 311. (Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04).

Watanabe, Minoru ; Kobayashi, Fuminori. / Timing analysis of an optically differential reconfigurable gate array for dynamically reconfigurable processors. Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04. editor / T.P. Plaks. 2004. pp. 311 (Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04).

@inproceedings{1b9ccd184883446388638d789fa03e91,

title = "Timing analysis of an optically differential reconfigurable gate array for dynamically reconfigurable processors",

abstract = "The timing analysis for reconfiguration and the execution of an optical differential reconfigurable gate array (ODRGA) for a dynamically reconfigurable processor was discussed. The reconfigurable timing was analyzed using a 0.35 μm CMOS process ODRGA-VLSI chip. The reconfiguration time of the ODRGA-VLSI chip was separated into three parts which were refresh time, detection time of the optical reconfiguration context, and the response time of differential reconfiguration circuits. It was found that the total time period necessary for optical reconfiguration and subsequent execution of the implementation circuit were 14.4 ns at 69 MHz.",

author = "Minoru Watanabe and Fuminori Kobayashi",

year = "2004",

language = "English",

isbn = "1932415424",

series = "Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04",

pages = "311",

editor = "T.P. Plaks",

booktitle = "Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04",

note = "Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04 ; Conference date: 21-06-2004 Through 24-06-2004",

}

TY - GEN

T1 - Timing analysis of an optically differential reconfigurable gate array for dynamically reconfigurable processors

AU - Watanabe, Minoru

AU - Kobayashi, Fuminori

PY - 2004

Y1 - 2004

N2 - The timing analysis for reconfiguration and the execution of an optical differential reconfigurable gate array (ODRGA) for a dynamically reconfigurable processor was discussed. The reconfigurable timing was analyzed using a 0.35 μm CMOS process ODRGA-VLSI chip. The reconfiguration time of the ODRGA-VLSI chip was separated into three parts which were refresh time, detection time of the optical reconfiguration context, and the response time of differential reconfiguration circuits. It was found that the total time period necessary for optical reconfiguration and subsequent execution of the implementation circuit were 14.4 ns at 69 MHz.

AB - The timing analysis for reconfiguration and the execution of an optical differential reconfigurable gate array (ODRGA) for a dynamically reconfigurable processor was discussed. The reconfigurable timing was analyzed using a 0.35 μm CMOS process ODRGA-VLSI chip. The reconfiguration time of the ODRGA-VLSI chip was separated into three parts which were refresh time, detection time of the optical reconfiguration context, and the response time of differential reconfiguration circuits. It was found that the total time period necessary for optical reconfiguration and subsequent execution of the implementation circuit were 14.4 ns at 69 MHz.

UR - http://www.scopus.com/inward/record.url?scp=12744263561&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=12744263561&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:12744263561

SN - 1932415424

SN - 9781932415421

T3 - Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04

SP - 311

BT - Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04

A2 - Plaks, T.P.

T2 - Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04

Y2 - 21 June 2004 through 24 June 2004

ER -

Timing analysis of an optically differential reconfigurable gate array for dynamically reconfigurable processors

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