Timing analysis of an optically differential reconfigurable gate array for dynamically reconfigurable processors

Minoru Watanabe, Fuminori Kobayashi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The timing analysis for reconfiguration and the execution of an optical differential reconfigurable gate array (ODRGA) for a dynamically reconfigurable processor was discussed. The reconfigurable timing was analyzed using a 0.35 μm CMOS process ODRGA-VLSI chip. The reconfiguration time of the ODRGA-VLSI chip was separated into three parts which were refresh time, detection time of the optical reconfiguration context, and the response time of differential reconfiguration circuits. It was found that the total time period necessary for optical reconfiguration and subsequent execution of the implementation circuit were 14.4 ns at 69 MHz.

Original languageEnglish
Title of host publicationProceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04
EditorsT.P. Plaks
Pages311
Number of pages1
Publication statusPublished - 2004
Externally publishedYes
EventProceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04 - Las Vegas, NV, United States
Duration: Jun 21 2004Jun 24 2004

Publication series

NameProceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04

Conference

ConferenceProceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04
Country/TerritoryUnited States
CityLas Vegas, NV
Period6/21/046/24/04

ASJC Scopus subject areas

  • Engineering(all)

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