TY - GEN
T1 - Timing analysis of an optically differential reconfigurable gate array for dynamically reconfigurable processors
AU - Watanabe, Minoru
AU - Kobayashi, Fuminori
PY - 2004
Y1 - 2004
N2 - The timing analysis for reconfiguration and the execution of an optical differential reconfigurable gate array (ODRGA) for a dynamically reconfigurable processor was discussed. The reconfigurable timing was analyzed using a 0.35 μm CMOS process ODRGA-VLSI chip. The reconfiguration time of the ODRGA-VLSI chip was separated into three parts which were refresh time, detection time of the optical reconfiguration context, and the response time of differential reconfiguration circuits. It was found that the total time period necessary for optical reconfiguration and subsequent execution of the implementation circuit were 14.4 ns at 69 MHz.
AB - The timing analysis for reconfiguration and the execution of an optical differential reconfigurable gate array (ODRGA) for a dynamically reconfigurable processor was discussed. The reconfigurable timing was analyzed using a 0.35 μm CMOS process ODRGA-VLSI chip. The reconfiguration time of the ODRGA-VLSI chip was separated into three parts which were refresh time, detection time of the optical reconfiguration context, and the response time of differential reconfiguration circuits. It was found that the total time period necessary for optical reconfiguration and subsequent execution of the implementation circuit were 14.4 ns at 69 MHz.
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M3 - Conference contribution
AN - SCOPUS:12744263561
SN - 1932415424
SN - 9781932415421
T3 - Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04
SP - 311
BT - Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04
A2 - Plaks, T.P.
T2 - Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04
Y2 - 21 June 2004 through 24 June 2004
ER -