Thin reduced graphene oxide interlayer with a conjugated block copolymer for high performance non-volatile ferroelectric polymer memory

Dhinesh Babu Velusamy, Richard Hahnkee Kim, Kazuto Takaishi, Tsuyoshi Muto, Daisuke Hashizume, Soyoon Lee, Masanobu Uchiyama, Tetsuya Aoyama, Jean Charles Ribierre, Cheolmin Park

Research output: Contribution to journalArticle

8 Citations (Scopus)

Abstract

Polymer ferroelectric-gate field effect transistors (Fe-FETs) employing ferroelectric polymer thin films as gate insulators are highly attractive as a next-generation non-volatile memory. For minimizing gate leakage current of a device which arises from electrically defective ferroelectric polymer layer in particular at low operation voltage, the materials design of interlayers between the ferroelectric insulator and gate electrode is essential. Here, we introduce a new solution-processed interlayer of conductive reduced graphene oxides (rGOs) modified with a conjugated block copolymer, poly(styrene-block- paraphenylene) (PS-b-PPP). A FeFET with a solution-processed p-type oligomeric semiconducting channel and ferroelectric poly(vinylidene fluoride-co- trifluoroethylene) (PVDF-TrFE) insulator exhibited characteristic source-drain current hysteresis arising from ferroelectric polarization switching of a PVDF-TrFE insulator. Our PS-b-PPP modified rGOs (PMrGOs) with conductive moieties embedded in insulating polymer matrix not only significantly reduced the gate leakage current but also efficiently lowered operation voltage of the device. In consequence, the device showed large memory gate voltage window and high ON/OFF source-drain current ratio with excellent data retention and read/write cycle endurance. Furthermore, our PMrGOs interlayers were successfully employed to FeFETs fabricated on mechanically flexible substrates with promising non-volatile memory performance under repetitive bending deformation.

Original languageEnglish
Pages (from-to)2719-2727
Number of pages9
JournalOrganic Electronics: physics, materials, applications
Volume15
Issue number11
DOIs
Publication statusPublished - 2014
Externally publishedYes

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block copolymers
Oxides
Graphene
Block copolymers
Ferroelectric materials
interlayers
graphene
Polymers
Data storage equipment
oxides
polymers
insulators
Drain current
vinylidene
Leakage currents
fluorides
Electric potential
electric potential
leakage

Keywords

  • Conjugated block copolymer
  • Ferroelectric polymer
  • Flexible non-volatile memory
  • Interlayer
  • Polymer ferroelectric-gate field effect transistor memory
  • Reduced graphene oxide

ASJC Scopus subject areas

  • Biomaterials
  • Electronic, Optical and Magnetic Materials
  • Materials Chemistry
  • Electrical and Electronic Engineering
  • Chemistry(all)
  • Condensed Matter Physics

Cite this

Thin reduced graphene oxide interlayer with a conjugated block copolymer for high performance non-volatile ferroelectric polymer memory. / Velusamy, Dhinesh Babu; Kim, Richard Hahnkee; Takaishi, Kazuto; Muto, Tsuyoshi; Hashizume, Daisuke; Lee, Soyoon; Uchiyama, Masanobu; Aoyama, Tetsuya; Ribierre, Jean Charles; Park, Cheolmin.

In: Organic Electronics: physics, materials, applications, Vol. 15, No. 11, 2014, p. 2719-2727.

Research output: Contribution to journalArticle

Velusamy, Dhinesh Babu ; Kim, Richard Hahnkee ; Takaishi, Kazuto ; Muto, Tsuyoshi ; Hashizume, Daisuke ; Lee, Soyoon ; Uchiyama, Masanobu ; Aoyama, Tetsuya ; Ribierre, Jean Charles ; Park, Cheolmin. / Thin reduced graphene oxide interlayer with a conjugated block copolymer for high performance non-volatile ferroelectric polymer memory. In: Organic Electronics: physics, materials, applications. 2014 ; Vol. 15, No. 11. pp. 2719-2727.
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AU - Muto, Tsuyoshi

AU - Hashizume, Daisuke

AU - Lee, Soyoon

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AU - Ribierre, Jean Charles

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AB - Polymer ferroelectric-gate field effect transistors (Fe-FETs) employing ferroelectric polymer thin films as gate insulators are highly attractive as a next-generation non-volatile memory. For minimizing gate leakage current of a device which arises from electrically defective ferroelectric polymer layer in particular at low operation voltage, the materials design of interlayers between the ferroelectric insulator and gate electrode is essential. Here, we introduce a new solution-processed interlayer of conductive reduced graphene oxides (rGOs) modified with a conjugated block copolymer, poly(styrene-block- paraphenylene) (PS-b-PPP). A FeFET with a solution-processed p-type oligomeric semiconducting channel and ferroelectric poly(vinylidene fluoride-co- trifluoroethylene) (PVDF-TrFE) insulator exhibited characteristic source-drain current hysteresis arising from ferroelectric polarization switching of a PVDF-TrFE insulator. Our PS-b-PPP modified rGOs (PMrGOs) with conductive moieties embedded in insulating polymer matrix not only significantly reduced the gate leakage current but also efficiently lowered operation voltage of the device. In consequence, the device showed large memory gate voltage window and high ON/OFF source-drain current ratio with excellent data retention and read/write cycle endurance. Furthermore, our PMrGOs interlayers were successfully employed to FeFETs fabricated on mechanically flexible substrates with promising non-volatile memory performance under repetitive bending deformation.

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