The data acquisition system of the belle silicon vertex detector (SVD) upgrade

H. Ishino, J. Kaneko, A. Kibayashi, H. Kurashiro, T. Mori, F. Ohno, K. Takahashi, Y. Watanabe, R. Abe, Y. Harada, H. Hirai, T. Kawasaki, H. Matsumoto, Y. Onuki, T. Shibata, N. Tamura, M. Watanabe, H. Yanai, T. Abe, H. AiharaK. Itoh, H. Kawai, A. Kusaka, T. Nakadaira, H. Tajima, T. Tomura, N. Uozaki, Y. Yamashita, M. Yokoyama, Y. Asano, A. Igarashi, S. Iwaida, Y. Nakano, S. Stanič, H. Terazaki, T. Aso, A. Bakich, L. Peak, K. Varvell, T. Browder, M. Rosen, K. Trabelsi, K. Uchida, G. Varner, M. C. Chang, Y. Chao, K. F. Chen, Z. W. Gao, W. C. Lin, K. Ueno, Y. S. Velikzhanin, C. C. Wang, M. Z. Wang, S. Chidzik, R. Fernholz, D. Marlow, R. Yang, T. Ziegler, J. Dalseno, R. Dowd, J. Dragic, C. W. Everton, A. Gordon, E. M. Heenan, A. Limosani, G. R. Moloney, G. N. Taylor, M. Friedl, R. Karawatzki, M. Pernicka, S. Schmid, H. Steininger, H. Fujii, J. Haba, T. Haruyama, K. Hayashi, M. Hazumi, T. Higuchi, N. Hitomi, Y. Igarashi, H. Ikeda, K. Kasami, S. Koike, R. Ohkubo, H. Ozaki, N. Sato, R. Stamen, J. Suzuki, F. Takasaki, M. Tanaka, T. Tsuboyama, K. Ueno, Y. Ushiroda, Y. Yamada, M. Yamauchi, Y. Yasu, Y. N. Guo, K. Hara, T. Hara, H. Miyake, K. Sumisawa, K. Hasuko, P. Kapusta, Z. Natkaniec, W. Ostrowicz, M. Rozanska, S. Korpar, P. Križan, D. Žontar, T. Lesiak, Y. Mikami, S. Nozaki, O. Tajima, H. Yamamoto, S. Okuno, W. Trischuk, S. Vahsen, Y. Yamashita

Research output: Contribution to journalArticle

Abstract

A newly developed data acquisition system (DAQ) for the upgraded silicon vertex detector (SVD2) in the Belle experiment is described. The system consists of 12 PCs connected through PCI I/O boards to 36 flash analog-to-digital converters (FADCs) to read out a system comprising a total of 110 592 strips. It is designed to cope with the increased number of readout channels and the maximum trigger rate of 1 kHz, foreseen in the future operation with higher beam currents. A measurement of the system performance using sparsification algorithm we have developed yields a 1.3-kHz readout rate for a 5% occupancy with less than 5% dead time, which satisfies the requirements on the maximum trigger rate.

Original languageEnglish
Pages (from-to)2064-2068
Number of pages5
JournalIEEE Transactions on Nuclear Science
Volume51
Issue number5 I
DOIs
Publication statusPublished - Oct 2004
Externally publishedYes

Keywords

  • Belle
  • Data acquisition
  • Silicon vertex detector

ASJC Scopus subject areas

  • Nuclear and High Energy Physics
  • Nuclear Energy and Engineering
  • Electrical and Electronic Engineering

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  • Cite this

    Ishino, H., Kaneko, J., Kibayashi, A., Kurashiro, H., Mori, T., Ohno, F., Takahashi, K., Watanabe, Y., Abe, R., Harada, Y., Hirai, H., Kawasaki, T., Matsumoto, H., Onuki, Y., Shibata, T., Tamura, N., Watanabe, M., Yanai, H., Abe, T., ... Yamashita, Y. (2004). The data acquisition system of the belle silicon vertex detector (SVD) upgrade. IEEE Transactions on Nuclear Science, 51(5 I), 2064-2068. https://doi.org/10.1109/TNS.2004.832649