Testing for the programming circuit of LUT-based FPGAs

H. Michinishi, Tokumi Yokohira, T. Okamoto, T. Inoue, H. Fujiwara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

Abstract

The programming circuit of look-up table based FPGAs consists of two shift registers, a control circuit and a configuration memory (SRAM) cell array. Because the configuration memory cell array can be easily tested by conventional test methods for RAMs, we focus on testing for the shift registers. We show that the testing can be done by using only the faculties of the programming circuit, without using additional hardware.

Original languageEnglish
Title of host publicationProceedings of the Asian Test Symposium
Pages242-247
Number of pages6
Publication statusPublished - 1997
EventProceedings of the 1997 6th Asian Test Symposium - Akita, Jpn
Duration: Nov 17 1997Nov 19 1997

Other

OtherProceedings of the 1997 6th Asian Test Symposium
CityAkita, Jpn
Period11/17/9711/19/97

    Fingerprint

ASJC Scopus subject areas

  • Media Technology
  • Hardware and Architecture

Cite this

Michinishi, H., Yokohira, T., Okamoto, T., Inoue, T., & Fujiwara, H. (1997). Testing for the programming circuit of LUT-based FPGAs. In Proceedings of the Asian Test Symposium (pp. 242-247)