Testing for the programming circuit of LUT-based FPGAs

H. Michinishi, T. Yokohira, T. Okamoto, T. Inoue, H. Fujiwara

Research output: Contribution to journalConference articlepeer-review

15 Citations (Scopus)

Abstract

The programming circuit of look-up table based FPGAs consists of two shift registers, a control circuit and a configuration memory (SRAM) cell array. Because the configuration memory cell array can be easily tested by conventional test methods for RAMs, we focus on testing for the shift registers. We show that the testing can be done by using only the faculties of the programming circuit, without using additional hardware.

Original languageEnglish
Pages (from-to)242-247
Number of pages6
JournalProceedings of the Asian Test Symposium
Publication statusPublished - Dec 1 1997
EventProceedings of the 1997 6th Asian Test Symposium - Akita, Jpn
Duration: Nov 17 1997Nov 19 1997

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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