In this paper, we consider testing for programmable interconnect structures of look-up table based FPGAs. The interconnect structure considered in the paper consists of interconnecting wires and programmable points (switches) to join them. As fault models, stuck-at faults of the wires, and extra-device faults and missing-device faults of the programmable points are considered. We heuristically derive test procedures for the faults and then show their validnesses and complexities.
|Number of pages||7|
|Journal||Proceedings of the Asian Test Symposium|
|Publication status||Published - Dec 1 1996|
|Event||Proceedings of the 1996 5th Asian Test Symposium, ATS'96 - Hsinchu, Taiwan|
Duration: Nov 20 1996 → Nov 22 1996
ASJC Scopus subject areas
- Electrical and Electronic Engineering