Test methodology for interconnect structures of LUT-based FPGAs

Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue, Hideo Fujiwara

Research output: Contribution to journalConference articlepeer-review

64 Citations (Scopus)


In this paper, we consider testing for programmable interconnect structures of look-up table based FPGAs. The interconnect structure considered in the paper consists of interconnecting wires and programmable points (switches) to join them. As fault models, stuck-at faults of the wires, and extra-device faults and missing-device faults of the programmable points are considered. We heuristically derive test procedures for the faults and then show their validnesses and complexities.

Original languageEnglish
Pages (from-to)68-74
Number of pages7
JournalProceedings of the Asian Test Symposium
Publication statusPublished - 1996
EventProceedings of the 1996 5th Asian Test Symposium, ATS'96 - Hsinchu, Taiwan
Duration: Nov 20 1996Nov 22 1996

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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