Test methodology for interconnect structures of LUT-based FPGAs

Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue, Hideo Fujiwara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

61 Citations (Scopus)

Abstract

In this paper, we consider testing for programmable interconnect structures of look-up table based FPGAs. The interconnect structure considered in the paper consists of interconnecting wires and programmable points (switches) to join them. As fault models, stuck-at faults of the wires, and extra-device faults and missing-device faults of the programmable points are considered. We heuristically derive test procedures for the faults and then show their validnesses and complexities.

Original languageEnglish
Title of host publicationProceedings of the Asian Test Symposium
Pages68-74
Number of pages7
Publication statusPublished - 1996
EventProceedings of the 1996 5th Asian Test Symposium, ATS'96 - Hsinchu, Taiwan
Duration: Nov 20 1996Nov 22 1996

Other

OtherProceedings of the 1996 5th Asian Test Symposium, ATS'96
CityHsinchu, Taiwan
Period11/20/9611/22/96

Fingerprint

Field programmable gate arrays (FPGA)
Wire
Switches
Testing

ASJC Scopus subject areas

  • Media Technology
  • Hardware and Architecture

Cite this

Michinishi, H., Yokohira, T., Okamoto, T., Inoue, T., & Fujiwara, H. (1996). Test methodology for interconnect structures of LUT-based FPGAs. In Proceedings of the Asian Test Symposium (pp. 68-74)

Test methodology for interconnect structures of LUT-based FPGAs. / Michinishi, Hiroyuki; Yokohira, Tokumi; Okamoto, Takuji; Inoue, Tomoo; Fujiwara, Hideo.

Proceedings of the Asian Test Symposium. 1996. p. 68-74.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Michinishi, H, Yokohira, T, Okamoto, T, Inoue, T & Fujiwara, H 1996, Test methodology for interconnect structures of LUT-based FPGAs. in Proceedings of the Asian Test Symposium. pp. 68-74, Proceedings of the 1996 5th Asian Test Symposium, ATS'96, Hsinchu, Taiwan, 11/20/96.
Michinishi H, Yokohira T, Okamoto T, Inoue T, Fujiwara H. Test methodology for interconnect structures of LUT-based FPGAs. In Proceedings of the Asian Test Symposium. 1996. p. 68-74
Michinishi, Hiroyuki ; Yokohira, Tokumi ; Okamoto, Takuji ; Inoue, Tomoo ; Fujiwara, Hideo. / Test methodology for interconnect structures of LUT-based FPGAs. Proceedings of the Asian Test Symposium. 1996. pp. 68-74
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