Systematic reducing of metastable operations in CMOS D flip-flops

Yoichiro Sato, Yoshinobu Yamasoto, Masanori Saito, Hiroto Kagotani, Takuji Okamoto, Masahiro Kawai

Research output: Contribution to journalArticle

Abstract

This paper systematically examines a method of reducing metastable (MS) operation in an edge-trigger type CMOS D flip-flop (EDFF) and a master-slave type D flip-flop (MDFF). To obtain a general idea, the mechanism of the MS operation of each flip-flop (FF) contained in the EDFF and MDFF has been classified into three types by using the results of a computer simulation. The first type MS operation is completely suppressed by the `differential threshold method' (in which the threshold voltage of the FF is different from that of the following circuit element so that the propagation of the MS operation is suppressed). An additional feedback method (by which the duration of the MS operation is reduced) is applied to the rest of the types of operations. A new circuit for these methods is also suggested. The computer simulation shows that the increase rate of MS-operation duration against the input-phase difference (difference between the occurrence time of a clock pulse and the occurrence time of an input) is reduced to about 1/4, and that the range of the input-phase difference of MS operations is reduced to about 1/3, in both EDFF and MDFF.

Original languageEnglish
Pages (from-to)20-28
Number of pages9
JournalSystems and Computers in Japan
Volume31
Issue number3
DOIs
Publication statusPublished - Mar 2000

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Flip flop circuits
Flip
Trigger
Phase Difference
Computer Simulation
Networks (circuits)
Computer simulation
Threshold voltage
Clocks
Voltage
Propagation
Feedback
Range of data

ASJC Scopus subject areas

  • Hardware and Architecture
  • Information Systems
  • Theoretical Computer Science
  • Computational Theory and Mathematics

Cite this

Systematic reducing of metastable operations in CMOS D flip-flops. / Sato, Yoichiro; Yamasoto, Yoshinobu; Saito, Masanori; Kagotani, Hiroto; Okamoto, Takuji; Kawai, Masahiro.

In: Systems and Computers in Japan, Vol. 31, No. 3, 03.2000, p. 20-28.

Research output: Contribution to journalArticle

Sato, Yoichiro ; Yamasoto, Yoshinobu ; Saito, Masanori ; Kagotani, Hiroto ; Okamoto, Takuji ; Kawai, Masahiro. / Systematic reducing of metastable operations in CMOS D flip-flops. In: Systems and Computers in Japan. 2000 ; Vol. 31, No. 3. pp. 20-28.
@article{16586cad62e84aeab2b3fc54803a9efb,
title = "Systematic reducing of metastable operations in CMOS D flip-flops",
abstract = "This paper systematically examines a method of reducing metastable (MS) operation in an edge-trigger type CMOS D flip-flop (EDFF) and a master-slave type D flip-flop (MDFF). To obtain a general idea, the mechanism of the MS operation of each flip-flop (FF) contained in the EDFF and MDFF has been classified into three types by using the results of a computer simulation. The first type MS operation is completely suppressed by the `differential threshold method' (in which the threshold voltage of the FF is different from that of the following circuit element so that the propagation of the MS operation is suppressed). An additional feedback method (by which the duration of the MS operation is reduced) is applied to the rest of the types of operations. A new circuit for these methods is also suggested. The computer simulation shows that the increase rate of MS-operation duration against the input-phase difference (difference between the occurrence time of a clock pulse and the occurrence time of an input) is reduced to about 1/4, and that the range of the input-phase difference of MS operations is reduced to about 1/3, in both EDFF and MDFF.",
author = "Yoichiro Sato and Yoshinobu Yamasoto and Masanori Saito and Hiroto Kagotani and Takuji Okamoto and Masahiro Kawai",
year = "2000",
month = "3",
doi = "10.1002/(SICI)1520-684X(200003)31:3<20::AID-SCJ3>3.0.CO;2-5",
language = "English",
volume = "31",
pages = "20--28",
journal = "Systems and Computers in Japan",
issn = "0882-1666",
publisher = "John Wiley and Sons Inc.",
number = "3",

}

TY - JOUR

T1 - Systematic reducing of metastable operations in CMOS D flip-flops

AU - Sato, Yoichiro

AU - Yamasoto, Yoshinobu

AU - Saito, Masanori

AU - Kagotani, Hiroto

AU - Okamoto, Takuji

AU - Kawai, Masahiro

PY - 2000/3

Y1 - 2000/3

N2 - This paper systematically examines a method of reducing metastable (MS) operation in an edge-trigger type CMOS D flip-flop (EDFF) and a master-slave type D flip-flop (MDFF). To obtain a general idea, the mechanism of the MS operation of each flip-flop (FF) contained in the EDFF and MDFF has been classified into three types by using the results of a computer simulation. The first type MS operation is completely suppressed by the `differential threshold method' (in which the threshold voltage of the FF is different from that of the following circuit element so that the propagation of the MS operation is suppressed). An additional feedback method (by which the duration of the MS operation is reduced) is applied to the rest of the types of operations. A new circuit for these methods is also suggested. The computer simulation shows that the increase rate of MS-operation duration against the input-phase difference (difference between the occurrence time of a clock pulse and the occurrence time of an input) is reduced to about 1/4, and that the range of the input-phase difference of MS operations is reduced to about 1/3, in both EDFF and MDFF.

AB - This paper systematically examines a method of reducing metastable (MS) operation in an edge-trigger type CMOS D flip-flop (EDFF) and a master-slave type D flip-flop (MDFF). To obtain a general idea, the mechanism of the MS operation of each flip-flop (FF) contained in the EDFF and MDFF has been classified into three types by using the results of a computer simulation. The first type MS operation is completely suppressed by the `differential threshold method' (in which the threshold voltage of the FF is different from that of the following circuit element so that the propagation of the MS operation is suppressed). An additional feedback method (by which the duration of the MS operation is reduced) is applied to the rest of the types of operations. A new circuit for these methods is also suggested. The computer simulation shows that the increase rate of MS-operation duration against the input-phase difference (difference between the occurrence time of a clock pulse and the occurrence time of an input) is reduced to about 1/4, and that the range of the input-phase difference of MS operations is reduced to about 1/3, in both EDFF and MDFF.

UR - http://www.scopus.com/inward/record.url?scp=0033875325&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0033875325&partnerID=8YFLogxK

U2 - 10.1002/(SICI)1520-684X(200003)31:3<20::AID-SCJ3>3.0.CO;2-5

DO - 10.1002/(SICI)1520-684X(200003)31:3<20::AID-SCJ3>3.0.CO;2-5

M3 - Article

AN - SCOPUS:0033875325

VL - 31

SP - 20

EP - 28

JO - Systems and Computers in Japan

JF - Systems and Computers in Japan

SN - 0882-1666

IS - 3

ER -