Abstract
An equivalent circuit model was applied to a cryptographic module to simulate the resistance of the module against side-channel attacks. The cryptographic module involved two fiel programmable gate arrays (FPGAs), on which an Advanced Encryption Standard (AES) circuit was implemented on one of them. The equivalent circuit model proposed in the previous literature was improved in terms of the accuracy of model parameters. Resistance against side-channel attacks was simulated in a more practical configuratio with the improved model than that in the previous work. Resistance was simulated with random plaintexts (input values) to the cryptographic circuit, whereas a biased plaintext set was used to simplify simulation. The simulation was carried out with two decoupling configuration for the power distribution network of the FPGA core that the AES circuit was implemented in. The results obtained from simulation confirme that the equivalent circuit model allowed side-channel resistance to be precisely predicted.
| Original language | English |
|---|---|
| Title of host publication | IEEE International Symposium on Electromagnetic Compatibility |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 224-229 |
| Number of pages | 6 |
| Volume | 2015-Septmber |
| ISBN (Print) | 9781479966158 |
| DOIs | |
| Publication status | Published - Sep 10 2015 |
| Event | IEEE International Symposium on Electromagnetic Compatibility, EMC 2015 - Dresden, Germany Duration: Aug 16 2015 → Aug 22 2015 |
Other
| Other | IEEE International Symposium on Electromagnetic Compatibility, EMC 2015 |
|---|---|
| Country | Germany |
| City | Dresden |
| Period | 8/16/15 → 8/22/15 |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Condensed Matter Physics
Cite this
Security simulation against side-channel attacks on Advanced Encryption Standard circuits based on equivalent circuit model. / Iokibe, Kengo; Maeshima, Kazuhiro; Watanabe, Tetsushi; Toyota, Yoshitaka.
IEEE International Symposium on Electromagnetic Compatibility. Vol. 2015-Septmber Institute of Electrical and Electronics Engineers Inc., 2015. p. 224-229 7256163.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Security simulation against side-channel attacks on Advanced Encryption Standard circuits based on equivalent circuit model
AU - Iokibe, Kengo
AU - Maeshima, Kazuhiro
AU - Watanabe, Tetsushi
AU - Toyota, Yoshitaka
PY - 2015/9/10
Y1 - 2015/9/10
N2 - An equivalent circuit model was applied to a cryptographic module to simulate the resistance of the module against side-channel attacks. The cryptographic module involved two fiel programmable gate arrays (FPGAs), on which an Advanced Encryption Standard (AES) circuit was implemented on one of them. The equivalent circuit model proposed in the previous literature was improved in terms of the accuracy of model parameters. Resistance against side-channel attacks was simulated in a more practical configuratio with the improved model than that in the previous work. Resistance was simulated with random plaintexts (input values) to the cryptographic circuit, whereas a biased plaintext set was used to simplify simulation. The simulation was carried out with two decoupling configuration for the power distribution network of the FPGA core that the AES circuit was implemented in. The results obtained from simulation confirme that the equivalent circuit model allowed side-channel resistance to be precisely predicted.
AB - An equivalent circuit model was applied to a cryptographic module to simulate the resistance of the module against side-channel attacks. The cryptographic module involved two fiel programmable gate arrays (FPGAs), on which an Advanced Encryption Standard (AES) circuit was implemented on one of them. The equivalent circuit model proposed in the previous literature was improved in terms of the accuracy of model parameters. Resistance against side-channel attacks was simulated in a more practical configuratio with the improved model than that in the previous work. Resistance was simulated with random plaintexts (input values) to the cryptographic circuit, whereas a biased plaintext set was used to simplify simulation. The simulation was carried out with two decoupling configuration for the power distribution network of the FPGA core that the AES circuit was implemented in. The results obtained from simulation confirme that the equivalent circuit model allowed side-channel resistance to be precisely predicted.
UR - http://www.scopus.com/inward/record.url?scp=84953847634&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84953847634&partnerID=8YFLogxK
U2 - 10.1109/ISEMC.2015.7256163
DO - 10.1109/ISEMC.2015.7256163
M3 - Conference contribution
AN - SCOPUS:84953847634
SN - 9781479966158
VL - 2015-Septmber
SP - 224
EP - 229
BT - IEEE International Symposium on Electromagnetic Compatibility
PB - Institute of Electrical and Electronics Engineers Inc.
ER -