Sampling rate conversion by Fourier interpolation

Manabu Inoue, Fuminori Kobayashi, Minoru Watanabe

Research output: Contribution to conferencePaperpeer-review

3 Citations (Scopus)

Abstract

New time-domain SRC using Fourier interpolation to achieve less gate count than in frequency domain is proposed and implemented by FPGA. Layout area of the proposed SRC based on a 0.35 μm process is 5.728mm2, smaller than the conventional SRC using filters. The noise level is reduced down to the quantizaion error level by using several improving methods.

Original languageEnglish
Pages523-526
Number of pages4
Publication statusPublished - 2004
Externally publishedYes
EventSICE Annual Conference 2004 - Sapporo, Japan
Duration: Aug 4 2004Aug 6 2004

Other

OtherSICE Annual Conference 2004
Country/TerritoryJapan
CitySapporo
Period8/4/048/6/04

Keywords

  • Digital audio
  • FPGA

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Computer Science Applications
  • Electrical and Electronic Engineering

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