Reduction of Stray Capacitance in an Inverter Main Circuit Using Multilayer Printed Circuit Boards

Kohsuke Ishikawa, Satoshi Ogasawara, Masatsugu Takemoto, Koji Orikawa

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper deals with stray capacitance in an inverter main circuit on a printed circuit board (PCB), which affects switching characteristics in a voltage source inverter (VSI), and reduction of the stray capacitance. A simulation shows that switching speed is decreased by the stray capacitance on the inverter output electrode pattern. The design guidelines focusing on reduction of the stray capacitance are proposed. Further, based on the guidelines, a SiC-MOSFET VSI to reduce the stray capacitance is designed using a double-sided PCB with 35 µm-thick standard copper foil. Experiments using SiC-MOSFET VSIs show that the inverter with the redesigned PCB shortens the switching time of the drain-source voltage by 10% for the rise time and by 38% for the fall time compared with an inverter based on our previous design guidelines. Hence, the switching loss is also reduced using the redesigned PCB inverter.

Original languageEnglish
Title of host publication2019 IEEE 4th International Future Energy Electronics Conference, IFEEC 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728131535
DOIs
Publication statusPublished - Nov 2019
Externally publishedYes
Event4th IEEE International Future Energy Electronics Conference, IFEEC 2019 - Singapore, Singapore
Duration: Nov 25 2019Nov 28 2019

Publication series

Name2019 IEEE 4th International Future Energy Electronics Conference, IFEEC 2019

Conference

Conference4th IEEE International Future Energy Electronics Conference, IFEEC 2019
CountrySingapore
CitySingapore
Period11/25/1911/28/19

Keywords

  • parasitic component
  • printed circuit board (PCB)
  • SiC-MOSFET
  • Stray capacitance
  • stray inductance

ASJC Scopus subject areas

  • Renewable Energy, Sustainability and the Environment
  • Electrical and Electronic Engineering
  • Energy Engineering and Power Technology

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  • Cite this

    Ishikawa, K., Ogasawara, S., Takemoto, M., & Orikawa, K. (2019). Reduction of Stray Capacitance in an Inverter Main Circuit Using Multilayer Printed Circuit Boards. In 2019 IEEE 4th International Future Energy Electronics Conference, IFEEC 2019 [9014917] (2019 IEEE 4th International Future Energy Electronics Conference, IFEEC 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IFEEC47410.2019.9014917