TY - GEN
T1 - Reduction of Stray Capacitance in an Inverter Main Circuit Using Multilayer Printed Circuit Boards
AU - Ishikawa, Kohsuke
AU - Ogasawara, Satoshi
AU - Takemoto, Masatsugu
AU - Orikawa, Koji
N1 - Funding Information:
This work was supported by Council for Science, Technology and Innovation (CSTI), Cross-ministerial Strategic Innovation Promotion Program (SIP), “Next-generation power electronics” (funding agency: NEDO)
Publisher Copyright:
© 2019 IEEE.
PY - 2019/11
Y1 - 2019/11
N2 - This paper deals with stray capacitance in an inverter main circuit on a printed circuit board (PCB), which affects switching characteristics in a voltage source inverter (VSI), and reduction of the stray capacitance. A simulation shows that switching speed is decreased by the stray capacitance on the inverter output electrode pattern. The design guidelines focusing on reduction of the stray capacitance are proposed. Further, based on the guidelines, a SiC-MOSFET VSI to reduce the stray capacitance is designed using a double-sided PCB with 35 µm-thick standard copper foil. Experiments using SiC-MOSFET VSIs show that the inverter with the redesigned PCB shortens the switching time of the drain-source voltage by 10% for the rise time and by 38% for the fall time compared with an inverter based on our previous design guidelines. Hence, the switching loss is also reduced using the redesigned PCB inverter.
AB - This paper deals with stray capacitance in an inverter main circuit on a printed circuit board (PCB), which affects switching characteristics in a voltage source inverter (VSI), and reduction of the stray capacitance. A simulation shows that switching speed is decreased by the stray capacitance on the inverter output electrode pattern. The design guidelines focusing on reduction of the stray capacitance are proposed. Further, based on the guidelines, a SiC-MOSFET VSI to reduce the stray capacitance is designed using a double-sided PCB with 35 µm-thick standard copper foil. Experiments using SiC-MOSFET VSIs show that the inverter with the redesigned PCB shortens the switching time of the drain-source voltage by 10% for the rise time and by 38% for the fall time compared with an inverter based on our previous design guidelines. Hence, the switching loss is also reduced using the redesigned PCB inverter.
KW - SiC-MOSFET
KW - Stray capacitance
KW - parasitic component
KW - printed circuit board (PCB)
KW - stray inductance
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U2 - 10.1109/IFEEC47410.2019.9014917
DO - 10.1109/IFEEC47410.2019.9014917
M3 - Conference contribution
AN - SCOPUS:85082381315
T3 - 2019 IEEE 4th International Future Energy Electronics Conference, IFEEC 2019
BT - 2019 IEEE 4th International Future Energy Electronics Conference, IFEEC 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 4th IEEE International Future Energy Electronics Conference, IFEEC 2019
Y2 - 25 November 2019 through 28 November 2019
ER -
