Reconfiguration performance analysis of a dynamic optically reconfigurable gate array architecture

Daisaku Seto, Minoru Watanabe

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

To increase gate density, a dynamic optically reconfigurable gate array (DORGA) architecture has been proposed that uses the junction capacitance of photodiodes as dynamic memory, thereby obviating the static configuration memory. However, to date, estimation ofa perfect optically reconfigurable architecture for DORGA-VLSIs has never been presented. This paper presents a perfect DORGA architecture including a holographic memory. The performances of the DORGA architecture, in particular the reconfiguration context retention time, were analyzed experimentally. The advantages of this architecture are discussed in relation to the results of this study.

Original languageEnglish
Title of host publicationICFPT 2007 - International Conference on Field Programmable Technology
Pages265-268
Number of pages4
DOIs
Publication statusPublished - 2007
Externally publishedYes
EventInternational Conference on Field Programmable Technology, ICFPT 2007 - Kitakyushu, Japan
Duration: Dec 12 2007Dec 14 2007

Publication series

NameICFPT 2007 - International Conference on Field Programmable Technology

Conference

ConferenceInternational Conference on Field Programmable Technology, ICFPT 2007
Country/TerritoryJapan
CityKitakyushu
Period12/12/0712/14/07

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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