Prevention of Oscillatory False Triggering of GaN-FETs by Balancing Gate-Drain Capacitance and Common Source Inductance

Kazuhiro Umetani, Ryunosuke Matsumoto, Eiji Hiraki

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

GaN-FETs are promising switching devices with fast switching capability. However, they commonly have low gate threshold voltage, suffering from susceptibility to the false triggering. Particularly, the oscillatory false triggering, i.e. a self-sustaining repetitive false triggering, can occur after a fast switching, which is severe obstacle for industry applications. The purpose of this paper is to elucidate the design instruction for preventing this phenomenon. The oscillatory false triggering is known to be caused by the parasitic oscillator circuit formed of a GaN-FET, its parasitic capacitance and the parasitic inductance of the wiring. This paper analyzed the non-oscillatory condition of this oscillator. The result revealed appropriate ratio between the gate-drain capacitance and the common source inductance is a key to prevent the oscillatory false triggering. Experiment successfully verified this analysis result, supporting the effectiveness of the appropriate design of this ratio for preventing the oscillatory false triggering.

Original languageEnglish
JournalIEEE Transactions on Industry Applications
DOIs
Publication statusAccepted/In press - Aug 31 2018

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Keywords

  • Common sourte induttante
  • False triggering
  • FET switthes
  • Inductance
  • Logic gates
  • Oscillators
  • Ostillator stability
  • Power semitonduttor devites
  • Resonant frequency
  • Switches
  • Threshold voltage
  • Wiring

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Industrial and Manufacturing Engineering
  • Electrical and Electronic Engineering

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