TY - GEN
T1 - Parasitic Inductance Design for Preventing Oscillatory False Triggering of Parallel-Connected GaN-FETs
AU - Hatakenaka, Yusuke
AU - Umetani, Kazuhiro
AU - Ishihara, Masataka
AU - Hiraki, Eiji
AU - Tadano, Hiroshi
N1 - Publisher Copyright:
© 2021 IEEE.
PY - 2021/10/13
Y1 - 2021/10/13
N2 - GaN-FETs are recently spreading in high-power switching converters, where GaN-FETs are commonly parallel connected to switch the large current. However, the parallel-connected GaN-FETs often suffer from false triggering because the parallel connection incorporates multiple LC resonators of the parasitic capacitance of GaN-FETs and the parasitic inductance of the printed circuit board, which can be easily excited by the switching noise and fluctuate the gate voltage. Particularly, GaN-FETs are susceptible to the self-sustaining repetition of the false triggering, i.e. the oscillatory false triggering, which must be prevented in industrial products. For prevention of this phenomenon in the case of a single GaN-FET, the preceding studies have proposed the design instruction of the parasitic inductance. However, few insights are available for the parallel-connected GaN-FETs. The purpose of this paper is to elucidate the design instruction to prevent the oscillatory false triggering for parallel-connected GaN-FETs through analyzing the equivalent circuit model of this phenomenon. The result revealed that parallel-connected GaN-FETs need the design instruction slightly modified from that for a single GaN-FET. The appropriateness of this modified instruction was verified by the simulation, suggesting the feasibility of this instruction for applying the parallel-connected GaN-FETs in high-power switching converters.
AB - GaN-FETs are recently spreading in high-power switching converters, where GaN-FETs are commonly parallel connected to switch the large current. However, the parallel-connected GaN-FETs often suffer from false triggering because the parallel connection incorporates multiple LC resonators of the parasitic capacitance of GaN-FETs and the parasitic inductance of the printed circuit board, which can be easily excited by the switching noise and fluctuate the gate voltage. Particularly, GaN-FETs are susceptible to the self-sustaining repetition of the false triggering, i.e. the oscillatory false triggering, which must be prevented in industrial products. For prevention of this phenomenon in the case of a single GaN-FET, the preceding studies have proposed the design instruction of the parasitic inductance. However, few insights are available for the parallel-connected GaN-FETs. The purpose of this paper is to elucidate the design instruction to prevent the oscillatory false triggering for parallel-connected GaN-FETs through analyzing the equivalent circuit model of this phenomenon. The result revealed that parallel-connected GaN-FETs need the design instruction slightly modified from that for a single GaN-FET. The appropriateness of this modified instruction was verified by the simulation, suggesting the feasibility of this instruction for applying the parallel-connected GaN-FETs in high-power switching converters.
KW - GaN-FET
KW - common-source inductance
KW - false triggering
KW - oscillatory false triggering
KW - parasitic inductance
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U2 - 10.1109/IECON48115.2021.9589541
DO - 10.1109/IECON48115.2021.9589541
M3 - Conference contribution
AN - SCOPUS:85119483066
T3 - IECON Proceedings (Industrial Electronics Conference)
BT - IECON 2021 - 47th Annual Conference of the IEEE Industrial Electronics Society
PB - IEEE Computer Society
T2 - 47th Annual Conference of the IEEE Industrial Electronics Society, IECON 2021
Y2 - 13 October 2021 through 16 October 2021
ER -