TY - GEN
T1 - Parallel implementations of lea, revisited
AU - Seo, Hwajeong
AU - Park, Taehwan
AU - Heo, Shinwook
AU - Seo, Gyuwon
AU - Bae, Bongjin
AU - Hu, Zhi
AU - Zhou, Lu
AU - Nogami, Yasuyuki
AU - Zhu, Youwen
AU - Kim, Howon
PY - 2017
Y1 - 2017
N2 - In this paper we revisited the parallel implementations of LEA. By taking the advantages of both the light-weight features of LEA and the parallel computation abilities of ARM-NEON platforms, performance is significantly improved. We firstly optimized the implementations on ARM and NEON architectures. For ARM processor, barrel shifter instruction is used to hide the latencies for rotation operations. For NEON engine, the minimum number of NEON registers are assigned to the round key variables by performing the on-time round key loading from ARM registers. This approach reduces the required NEON registers for round key variables by three registers and the registers and temporal registers are used to retain four more plaintext for encryption operation. Furthermore, we finely transform the data into SIMD format by using transpose and swap instructions. The compact ARM and NEON implementations are combined together and computed in mixed processing way. This approach hides the latency of ARM computations into NEON overheads. Finally, multiple cores are fully exploited to perform the maximum throughputs on the target devices. The proposed implementations achieved the fastest LEA encryption within 3.2 cycle/byte for Cortex-A9 processors.
AB - In this paper we revisited the parallel implementations of LEA. By taking the advantages of both the light-weight features of LEA and the parallel computation abilities of ARM-NEON platforms, performance is significantly improved. We firstly optimized the implementations on ARM and NEON architectures. For ARM processor, barrel shifter instruction is used to hide the latencies for rotation operations. For NEON engine, the minimum number of NEON registers are assigned to the round key variables by performing the on-time round key loading from ARM registers. This approach reduces the required NEON registers for round key variables by three registers and the registers and temporal registers are used to retain four more plaintext for encryption operation. Furthermore, we finely transform the data into SIMD format by using transpose and swap instructions. The compact ARM and NEON implementations are combined together and computed in mixed processing way. This approach hides the latency of ARM computations into NEON overheads. Finally, multiple cores are fully exploited to perform the maximum throughputs on the target devices. The proposed implementations achieved the fastest LEA encryption within 3.2 cycle/byte for Cortex-A9 processors.
KW - ARM
KW - Lightweight Encryption Algorithm
KW - NEON
KW - OpenMP
KW - Parallel implementation
UR - http://www.scopus.com/inward/record.url?scp=85017579944&partnerID=8YFLogxK
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U2 - 10.1007/978-3-319-56549-1_27
DO - 10.1007/978-3-319-56549-1_27
M3 - Conference contribution
AN - SCOPUS:85017579944
SN - 9783319565484
VL - 10144 LNCS
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 318
EP - 330
BT - Information Security Applications - 17th International Workshop, WISA 2016, Revised Selected Papers
PB - Springer Verlag
T2 - 17th International Workshop on Information Security Applications, WISA 2016
Y2 - 25 August 2016 through 25 August 2016
ER -