TY - GEN
T1 - Optimization of Common Source Inductance and Gate-Drain Capacitance for Reducing Gate Voltage Fluctuation after Turn-off Transition
AU - Hatakenaka, Yusuke
AU - Umetani, Kazuhiro
AU - Ishihara, Masataka
AU - Hiraki, Eiji
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/10/11
Y1 - 2020/10/11
N2 - Next-generation switching devices as GaN-FETs are recently emerging as promising switching devices capable of extremely high-speed switching. High-speed switching enables the high-frequency operation of the power converters, which can reduce the size of the passive components. However, high-speed switching can induce the resonance between the parasitic capacitance of the switching device and the parasitic inductance of the circuit board wiring, which appears as the gate voltage fluctuation at the switching. Particularly, GaN-FETs tend to have comparatively low gate threshold voltage and therefore are susceptible to the false turn-on, which is caused by the gate voltage fluctuation in the switching device just after the turn-off transition. For preventing this phenomenon, this paper analytically investigates the design requirement of these parasitic parameters to reduce the gate voltage fluctuation after the turn-off transition. As a result, the optimal ratio of the gate-drain capacitance and the common source inductance is elucidated to be the key to minimize the gate voltage fluctuation. The simulation and the experiment supported that the optimal design of this ratio can reduce the gate voltage fluctuation, supporting the usefulness of this novel insight for preventing the false turn-on.
AB - Next-generation switching devices as GaN-FETs are recently emerging as promising switching devices capable of extremely high-speed switching. High-speed switching enables the high-frequency operation of the power converters, which can reduce the size of the passive components. However, high-speed switching can induce the resonance between the parasitic capacitance of the switching device and the parasitic inductance of the circuit board wiring, which appears as the gate voltage fluctuation at the switching. Particularly, GaN-FETs tend to have comparatively low gate threshold voltage and therefore are susceptible to the false turn-on, which is caused by the gate voltage fluctuation in the switching device just after the turn-off transition. For preventing this phenomenon, this paper analytically investigates the design requirement of these parasitic parameters to reduce the gate voltage fluctuation after the turn-off transition. As a result, the optimal ratio of the gate-drain capacitance and the common source inductance is elucidated to be the key to minimize the gate voltage fluctuation. The simulation and the experiment supported that the optimal design of this ratio can reduce the gate voltage fluctuation, supporting the usefulness of this novel insight for preventing the false turn-on.
KW - GaN-FET
KW - common source inductance
KW - false triggering
KW - parasitic capacitance
KW - self-turn-on
KW - switching noise
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U2 - 10.1109/ECCE44975.2020.9236428
DO - 10.1109/ECCE44975.2020.9236428
M3 - Conference contribution
AN - SCOPUS:85097171938
T3 - ECCE 2020 - IEEE Energy Conversion Congress and Exposition
SP - 3155
EP - 3162
BT - ECCE 2020 - IEEE Energy Conversion Congress and Exposition
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 12th Annual IEEE Energy Conversion Congress and Exposition, ECCE 2020
Y2 - 11 October 2020 through 15 October 2020
ER -