TY - GEN
T1 - Optically reconfigurable gate array platform for mono-instruction set computer architecture
AU - Shimba, Hiroki
AU - Watanabe, Minoru
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/3/1
Y1 - 2017/3/1
N2 - The operating clock frequency of the latest processor has never been increased because of recent process issues. A game change must occur to achieve progress in clock frequencies. Therefore, we propose a mono-instruction set computer (MISC) architecture based on optically reconfigurable gate array architecture. The MISC architecture consists of various single instruction processor cores having only one instruction. Using the MISC architecture, the processor performance can be increased drastically. However, the only requirement is the use of a high-speed dynamically reconfigurable device or an optically reconfigurable gate array (ORGA). As described herein, we present the latest ORGA and discuss benefits of MISC architecture based on the ORGA.
AB - The operating clock frequency of the latest processor has never been increased because of recent process issues. A game change must occur to achieve progress in clock frequencies. Therefore, we propose a mono-instruction set computer (MISC) architecture based on optically reconfigurable gate array architecture. The MISC architecture consists of various single instruction processor cores having only one instruction. Using the MISC architecture, the processor performance can be increased drastically. However, the only requirement is the use of a high-speed dynamically reconfigurable device or an optically reconfigurable gate array (ORGA). As described herein, we present the latest ORGA and discuss benefits of MISC architecture based on the ORGA.
UR - http://www.scopus.com/inward/record.url?scp=85016801424&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85016801424&partnerID=8YFLogxK
U2 - 10.1109/CCWC.2017.7868473
DO - 10.1109/CCWC.2017.7868473
M3 - Conference contribution
AN - SCOPUS:85016801424
T3 - 2017 IEEE 7th Annual Computing and Communication Workshop and Conference, CCWC 2017
BT - 2017 IEEE 7th Annual Computing and Communication Workshop and Conference, CCWC 2017
A2 - Saha, Himadri Nath
A2 - Chakrabarti, Satyajit
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 7th IEEE Annual Computing and Communication Workshop and Conference, CCWC 2017
Y2 - 9 January 2017 through 11 January 2017
ER -