Optically reconfigurable gate array platform for mono-instruction set computer architecture

Hiroki Shimba, Minoru Watanabe

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

The operating clock frequency of the latest processor has never been increased because of recent process issues. A game change must occur to achieve progress in clock frequencies. Therefore, we propose a mono-instruction set computer (MISC) architecture based on optically reconfigurable gate array architecture. The MISC architecture consists of various single instruction processor cores having only one instruction. Using the MISC architecture, the processor performance can be increased drastically. However, the only requirement is the use of a high-speed dynamically reconfigurable device or an optically reconfigurable gate array (ORGA). As described herein, we present the latest ORGA and discuss benefits of MISC architecture based on the ORGA.

Original languageEnglish
Title of host publication2017 IEEE 7th Annual Computing and Communication Workshop and Conference, CCWC 2017
EditorsHimadri Nath Saha, Satyajit Chakrabarti
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509042289
DOIs
Publication statusPublished - Mar 1 2017
Externally publishedYes
Event7th IEEE Annual Computing and Communication Workshop and Conference, CCWC 2017 - Las Vegas, United States
Duration: Jan 9 2017Jan 11 2017

Publication series

Name2017 IEEE 7th Annual Computing and Communication Workshop and Conference, CCWC 2017

Conference

Conference7th IEEE Annual Computing and Communication Workshop and Conference, CCWC 2017
Country/TerritoryUnited States
CityLas Vegas
Period1/9/171/11/17

ASJC Scopus subject areas

  • Computer Networks and Communications

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