Optically reconfigurable gate array platform for mono-instruction set computer architecture

Hiroki Shimba; Minoru Watanabe

doi:10.1109/CCWC.2017.7868473

Optically reconfigurable gate array platform for mono-instruction set computer architecture

Hiroki Shimba, Minoru Watanabe

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

The operating clock frequency of the latest processor has never been increased because of recent process issues. A game change must occur to achieve progress in clock frequencies. Therefore, we propose a mono-instruction set computer (MISC) architecture based on optically reconfigurable gate array architecture. The MISC architecture consists of various single instruction processor cores having only one instruction. Using the MISC architecture, the processor performance can be increased drastically. However, the only requirement is the use of a high-speed dynamically reconfigurable device or an optically reconfigurable gate array (ORGA). As described herein, we present the latest ORGA and discuss benefits of MISC architecture based on the ORGA.

Original language	English
Title of host publication	2017 IEEE 7th Annual Computing and Communication Workshop and Conference, CCWC 2017
Editors	Himadri Nath Saha, Satyajit Chakrabarti
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509042289
DOIs	https://doi.org/10.1109/CCWC.2017.7868473
Publication status	Published - Mar 1 2017
Externally published	Yes
Event	7th IEEE Annual Computing and Communication Workshop and Conference, CCWC 2017 - Las Vegas, United States Duration: Jan 9 2017 → Jan 11 2017

Publication series

Name	2017 IEEE 7th Annual Computing and Communication Workshop and Conference, CCWC 2017

Conference

Conference	7th IEEE Annual Computing and Communication Workshop and Conference, CCWC 2017
Country/Territory	United States
City	Las Vegas
Period	1/9/17 → 1/11/17

ASJC Scopus subject areas

Computer Networks and Communications

Access to Document

10.1109/CCWC.2017.7868473

Cite this

Shimba, H., & Watanabe, M. (2017). Optically reconfigurable gate array platform for mono-instruction set computer architecture. In H. N. Saha, & S. Chakrabarti (Eds.), 2017 IEEE 7th Annual Computing and Communication Workshop and Conference, CCWC 2017 [7868473] (2017 IEEE 7th Annual Computing and Communication Workshop and Conference, CCWC 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CCWC.2017.7868473

Optically reconfigurable gate array platform for mono-instruction set computer architecture. / Shimba, Hiroki; Watanabe, Minoru.

2017 IEEE 7th Annual Computing and Communication Workshop and Conference, CCWC 2017. ed. / Himadri Nath Saha; Satyajit Chakrabarti. Institute of Electrical and Electronics Engineers Inc., 2017. 7868473 (2017 IEEE 7th Annual Computing and Communication Workshop and Conference, CCWC 2017).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Shimba, H & Watanabe, M 2017, Optically reconfigurable gate array platform for mono-instruction set computer architecture. in HN Saha & S Chakrabarti (eds), 2017 IEEE 7th Annual Computing and Communication Workshop and Conference, CCWC 2017., 7868473, 2017 IEEE 7th Annual Computing and Communication Workshop and Conference, CCWC 2017, Institute of Electrical and Electronics Engineers Inc., 7th IEEE Annual Computing and Communication Workshop and Conference, CCWC 2017, Las Vegas, United States, 1/9/17. https://doi.org/10.1109/CCWC.2017.7868473

Shimba H, Watanabe M. Optically reconfigurable gate array platform for mono-instruction set computer architecture. In Saha HN, Chakrabarti S, editors, 2017 IEEE 7th Annual Computing and Communication Workshop and Conference, CCWC 2017. Institute of Electrical and Electronics Engineers Inc. 2017. 7868473. (2017 IEEE 7th Annual Computing and Communication Workshop and Conference, CCWC 2017). https://doi.org/10.1109/CCWC.2017.7868473

Shimba, Hiroki ; Watanabe, Minoru. / Optically reconfigurable gate array platform for mono-instruction set computer architecture. 2017 IEEE 7th Annual Computing and Communication Workshop and Conference, CCWC 2017. editor / Himadri Nath Saha ; Satyajit Chakrabarti. Institute of Electrical and Electronics Engineers Inc., 2017. (2017 IEEE 7th Annual Computing and Communication Workshop and Conference, CCWC 2017).

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Optically reconfigurable gate array platform for mono-instruction set computer architecture

Abstract

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ASJC Scopus subject areas

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