Optical configuration of an 11,424 gate-count dynamic optically reconfigurable gate array using a VCSEL

Daisaku Seto, Minora Watanabe

Research output: Contribution to conferencePaperpeer-review

Abstract

Recently, to realize large real-time systems, demands for fast computation on large VLSI have continued to increase. An optically reconfigurable gate array has been developed to realize large virtual gates. As part of that research effort, the world's largest 11,424 gate-count dynamic optically reconfigurable gate array VLSI chip, which is based on a concept using junction capacitance of photodiodes as configuration memory, has been fabricated. The size and process of the VLSI chip are, respectively, a 96.04 mm2 and a 0.35 μ-3 metal CMOS process technology. To clarify the availability of the VLSI, this paper presents an experimental result of a long retention time of its photodiode memory architecture.

Original languageEnglish
Pages95-99
Number of pages5
DOIs
Publication statusPublished - 2008
Externally publishedYes
Event2008 IEEE/SICE International Symposium on System Integration: SI International 2008 - The 1st Symposium on Systems Integration - Nagoya, Japan
Duration: Dec 4 2008Dec 4 2008

Conference

Conference2008 IEEE/SICE International Symposium on System Integration: SI International 2008 - The 1st Symposium on Systems Integration
Country/TerritoryJapan
CityNagoya
Period12/4/0812/4/08

Keywords

  • CPLDs
  • FPGAs
  • ORGAs

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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