Non-feedback neuron filter algorithm for separated board-level routing problems in FPGA-based logic emulation systems

Yoichi Takenaka, Nobuo Funabiki

Research output: Contribution to conferencePaper

Abstract

This paper presents a neuron filter algorithm to satisfy two constraints of the graph-coloring problem through a separated board-level routing problem (s-BLRP) in an FPGA-based logic emulation system. For a rapid prototyping of large scale digital systems, multiple FPGA's provide an efficient logic emulation system, where signals or nets between design partitions embedded on different FPGA's are connected through crossbars. We propose a new neuron filter algorithm to satisfy the two constraints of the problem simultaneously. The simulation results in randomly generated benchmark size instances show that our neuron filter algorithm with the thinning out application provides the better routing capability with the shorter computation time.

Original languageEnglish
Pages3342-3347
Number of pages6
Publication statusPublished - 1999
EventInternational Joint Conference on Neural Networks (IJCNN'99) - Washington, DC, USA
Duration: Jul 10 1999Jul 16 1999

Other

OtherInternational Joint Conference on Neural Networks (IJCNN'99)
CityWashington, DC, USA
Period7/10/997/16/99

ASJC Scopus subject areas

  • Software
  • Artificial Intelligence

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    Takenaka, Y., & Funabiki, N. (1999). Non-feedback neuron filter algorithm for separated board-level routing problems in FPGA-based logic emulation systems. 3342-3347. Paper presented at International Joint Conference on Neural Networks (IJCNN'99), Washington, DC, USA, .