Network processor for high-speed network and quick programming

Takahiro Murooka, Akira Nagoya, Toshiaki Miyazaki, Hiroyuki Ochi, Yukihiro Nakamura

Research output: Contribution to journalArticle

Abstract

The paper describes the concept, architecture, and prototype test results of a packet processor that enables us to implement an application-specific high-speed packet processing system without expert-level programming skills. This processor has a pipelined processing architecture and features coarse-grained instructions that are based on the data formats of the telecommunication packet. Using this processor, target applications can be implemented within a short working period without degrading the processing performance. We implemented a prototype system to evaluate its packet propagation delay and packet forwarding performance. The measured results suggest that the architecture is useful for packet processing on high-speed telecommunication networks.

Original languageEnglish
Pages (from-to)65-79
Number of pages15
JournalJournal of Circuits, Systems and Computers
Volume16
Issue number1
DOIs
Publication statusPublished - Feb 2007

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HIgh speed networks
Computer networks
Computer programming
Program processors
Processing
Expert systems
Telecommunication networks
Telecommunication

Keywords

  • Active network
  • Packet processing
  • Processor architecture

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture

Cite this

Network processor for high-speed network and quick programming. / Murooka, Takahiro; Nagoya, Akira; Miyazaki, Toshiaki; Ochi, Hiroyuki; Nakamura, Yukihiro.

In: Journal of Circuits, Systems and Computers, Vol. 16, No. 1, 02.2007, p. 65-79.

Research output: Contribution to journalArticle

Murooka, Takahiro ; Nagoya, Akira ; Miyazaki, Toshiaki ; Ochi, Hiroyuki ; Nakamura, Yukihiro. / Network processor for high-speed network and quick programming. In: Journal of Circuits, Systems and Computers. 2007 ; Vol. 16, No. 1. pp. 65-79.
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