Multi-level logic optimization for large scale ASICs

Akira Nagoya, Yukihiro Nakamura, Kiyoshi Oguri, Ryo Nomura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

The authors developed an efficient high-level synthesis and optimization system for large-scale circuits, which reduces the total number of fan-ins in the technology-independent phase and adjusts speed and area after technology mapping is completed. A description is presented of multi-level logic optimization techniques based on refined weak division methods and additional functions for carrying out good optimization with only a slight overhead. The authors also describe technology mapping and local optimization techniques suitable for high-level CAD systems. The system has shown that multi-level logic optimization in VLSIs with more than 100,000 gates (that is, VLSIs whose control logic comprises more than 10,000 gate circuits) is possible in practical CPU time.

Original languageEnglish
Title of host publication1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers
PublisherPubl by IEEE
Pages564-567
Number of pages4
ISBN (Print)0818620552
Publication statusPublished - 1990
Externally publishedYes
Event1990 IEEE International Conference on Computer-Aided Design - ICCAD-90 - Santa Clara, CA, USA
Duration: Nov 11 1990Nov 15 1990

Other

Other1990 IEEE International Conference on Computer-Aided Design - ICCAD-90
CitySanta Clara, CA, USA
Period11/11/9011/15/90

Fingerprint

Application specific integrated circuits
Networks (circuits)
Program processors
Computer aided design

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Nagoya, A., Nakamura, Y., Oguri, K., & Nomura, R. (1990). Multi-level logic optimization for large scale ASICs. In 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers (pp. 564-567). Publ by IEEE.

Multi-level logic optimization for large scale ASICs. / Nagoya, Akira; Nakamura, Yukihiro; Oguri, Kiyoshi; Nomura, Ryo.

1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers. Publ by IEEE, 1990. p. 564-567.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Nagoya, A, Nakamura, Y, Oguri, K & Nomura, R 1990, Multi-level logic optimization for large scale ASICs. in 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers. Publ by IEEE, pp. 564-567, 1990 IEEE International Conference on Computer-Aided Design - ICCAD-90, Santa Clara, CA, USA, 11/11/90.
Nagoya A, Nakamura Y, Oguri K, Nomura R. Multi-level logic optimization for large scale ASICs. In 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers. Publ by IEEE. 1990. p. 564-567
Nagoya, Akira ; Nakamura, Yukihiro ; Oguri, Kiyoshi ; Nomura, Ryo. / Multi-level logic optimization for large scale ASICs. 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers. Publ by IEEE, 1990. pp. 564-567
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