Mono-instruction set computer architecture on a 3D optically reconfigurable gate array

Hiroyuki Ito, Minoru Watanabe

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Currently, three-dimensional VLSI technologies are being developed. However, by increasing the number of layers of TSV or stacking layers, the production difficulty of VLSI is increased. Therefore, optically reconfigurable gate arrays (ORGAs) have been developed to realize high-speed dynamic reconfiguration. The ORGA consists of a holographic memory, a programmable gate array, and a laser array. An ORGA can store large amounts of circuit information inside a holographic memory. The circuit information can be programmed dynamically onto an ORGA's programmable gate array in nanosecond-order. The ORGA allows high-speed dynamic reconfiguration. If the high-speed dynamic reconfiguration can be used for the implementation of processors, then the processor performance can be increased. The implementation technique is called a mono-instruction set computer (MISC) architecture. This paper presents a demonstration result of a high-performance MISC architecture that fully exploits the high-speed programmability of an ORGA.

Original languageEnglish
Title of host publicationEDAPS 2013 - 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium
Pages173-176
Number of pages4
DOIs
Publication statusPublished - 2013
Externally publishedYes
Event2013 6th IEEE Electrical Design of Advanced Packaging Systems Symposium, EDAPS 2013 - Nara, Japan
Duration: Dec 12 2013Dec 15 2013

Publication series

NameEDAPS 2013 - 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium

Other

Other2013 6th IEEE Electrical Design of Advanced Packaging Systems Symposium, EDAPS 2013
Country/TerritoryJapan
CityNara
Period12/12/1312/15/13

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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