TY - GEN
T1 - Mono-instruction set computer architecture on a 3D optically reconfigurable gate array
AU - Ito, Hiroyuki
AU - Watanabe, Minoru
PY - 2013
Y1 - 2013
N2 - Currently, three-dimensional VLSI technologies are being developed. However, by increasing the number of layers of TSV or stacking layers, the production difficulty of VLSI is increased. Therefore, optically reconfigurable gate arrays (ORGAs) have been developed to realize high-speed dynamic reconfiguration. The ORGA consists of a holographic memory, a programmable gate array, and a laser array. An ORGA can store large amounts of circuit information inside a holographic memory. The circuit information can be programmed dynamically onto an ORGA's programmable gate array in nanosecond-order. The ORGA allows high-speed dynamic reconfiguration. If the high-speed dynamic reconfiguration can be used for the implementation of processors, then the processor performance can be increased. The implementation technique is called a mono-instruction set computer (MISC) architecture. This paper presents a demonstration result of a high-performance MISC architecture that fully exploits the high-speed programmability of an ORGA.
AB - Currently, three-dimensional VLSI technologies are being developed. However, by increasing the number of layers of TSV or stacking layers, the production difficulty of VLSI is increased. Therefore, optically reconfigurable gate arrays (ORGAs) have been developed to realize high-speed dynamic reconfiguration. The ORGA consists of a holographic memory, a programmable gate array, and a laser array. An ORGA can store large amounts of circuit information inside a holographic memory. The circuit information can be programmed dynamically onto an ORGA's programmable gate array in nanosecond-order. The ORGA allows high-speed dynamic reconfiguration. If the high-speed dynamic reconfiguration can be used for the implementation of processors, then the processor performance can be increased. The implementation technique is called a mono-instruction set computer (MISC) architecture. This paper presents a demonstration result of a high-performance MISC architecture that fully exploits the high-speed programmability of an ORGA.
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U2 - 10.1109/EDAPS.2013.6724417
DO - 10.1109/EDAPS.2013.6724417
M3 - Conference contribution
AN - SCOPUS:84894122037
SN - 9781479923113
T3 - EDAPS 2013 - 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium
SP - 173
EP - 176
BT - EDAPS 2013 - 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium
T2 - 2013 6th IEEE Electrical Design of Advanced Packaging Systems Symposium, EDAPS 2013
Y2 - 12 December 2013 through 15 December 2013
ER -