Modeling and simulation of via-connected power bus stacks in multilayer PCBs

Zhi Liang Wang; Osami Wada; Takashi Harada; Takahiro Yaguchi; Yoshitaka Toyota; Ryuji Koga

doi:10.1093/ietcom/e88-b.8.3176

Modeling and simulation of via-connected power bus stacks in multilayer PCBs

Zhi Liang Wang, Osami Wada, Takashi Harada, Takahiro Yaguchi, Yoshitaka Toyota, Ryuji Koga

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

Power bus noise problem has become a major concern for both EMC engineers and board designers. A fast algorithm, based on the cavity-mode model, was employed for analyzing resonance characteristics of multilayer power bus stacks interconnected by vias. The via is modeled as an inductance and its value is given by a simple expression. Good agreement between the simulated results and measurements demonstrates the effectiveness of the cavity-mode model, together with the via model.

Original language	English
Pages (from-to)	3176-3181
Number of pages	6
Journal	IEICE Transactions on Communications
Volume	E88-B
Issue number	8
DOIs	https://doi.org/10.1093/ietcom/e88-b.8.3176
Publication status	Published - Aug 2005

Keywords

Cavity-mode model
EMI
Power bus stack and modeling
Via interconnect

ASJC Scopus subject areas

Software
Computer Networks and Communications
Electrical and Electronic Engineering

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10.1093/ietcom/e88-b.8.3176

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title = "Modeling and simulation of via-connected power bus stacks in multilayer PCBs",

abstract = "Power bus noise problem has become a major concern for both EMC engineers and board designers. A fast algorithm, based on the cavity-mode model, was employed for analyzing resonance characteristics of multilayer power bus stacks interconnected by vias. The via is modeled as an inductance and its value is given by a simple expression. Good agreement between the simulated results and measurements demonstrates the effectiveness of the cavity-mode model, together with the via model.",

keywords = "Cavity-mode model, EMI, Power bus stack and modeling, Via interconnect",

author = "Wang, {Zhi Liang} and Osami Wada and Takashi Harada and Takahiro Yaguchi and Yoshitaka Toyota and Ryuji Koga",

year = "2005",

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AU - Wang, Zhi Liang

AU - Wada, Osami

AU - Harada, Takashi

AU - Yaguchi, Takahiro

AU - Toyota, Yoshitaka

AU - Koga, Ryuji

PY - 2005/8

Y1 - 2005/8

N2 - Power bus noise problem has become a major concern for both EMC engineers and board designers. A fast algorithm, based on the cavity-mode model, was employed for analyzing resonance characteristics of multilayer power bus stacks interconnected by vias. The via is modeled as an inductance and its value is given by a simple expression. Good agreement between the simulated results and measurements demonstrates the effectiveness of the cavity-mode model, together with the via model.

AB - Power bus noise problem has become a major concern for both EMC engineers and board designers. A fast algorithm, based on the cavity-mode model, was employed for analyzing resonance characteristics of multilayer power bus stacks interconnected by vias. The via is modeled as an inductance and its value is given by a simple expression. Good agreement between the simulated results and measurements demonstrates the effectiveness of the cavity-mode model, together with the via model.

KW - Cavity-mode model

KW - EMI

KW - Power bus stack and modeling

KW - Via interconnect

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JO - IEICE Transactions on Communications

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Modeling and simulation of via-connected power bus stacks in multilayer PCBs

Abstract

Keywords

ASJC Scopus subject areas

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