LUT-based FPGA technology mapping using permissible functions

Takayuki Suyama, Hiroshi Sawada, Akira Nagoya

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper we present a method that maps a loop-free multilevel combinational circuit into Look-Up Table (LUT) based Field Programmable Gate Arrays (FPGAs) using permissible functions. When mapping a minimized circuit into LUTs, a characteristic difference between an LUT and simple gates causes ineffective use of the LUT. Using permissible functions, the circuit is adroitly adapted for an LUT that has n inputs, one output, and can implement any n-variable Boolean function. We have implemented this method and carried out some experiments. Results show that this method is useful to refine initial mapping to LUTs.

Original languageEnglish
Title of host publicationProceedings of the IEEE International Conference on VLSI Design
PublisherIEEE
Pages215-218
Number of pages4
Publication statusPublished - 1996
Externally publishedYes
EventProceedings of the 1996 9th International Conference on VLSI Design - Bangalore, India
Duration: Jan 3 1996Jan 6 1996

Other

OtherProceedings of the 1996 9th International Conference on VLSI Design
CityBangalore, India
Period1/3/961/6/96

Fingerprint

Field programmable gate arrays (FPGA)
Combinatorial circuits
Boolean functions
Networks (circuits)
Experiments

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Suyama, T., Sawada, H., & Nagoya, A. (1996). LUT-based FPGA technology mapping using permissible functions. In Proceedings of the IEEE International Conference on VLSI Design (pp. 215-218). IEEE.

LUT-based FPGA technology mapping using permissible functions. / Suyama, Takayuki; Sawada, Hiroshi; Nagoya, Akira.

Proceedings of the IEEE International Conference on VLSI Design. IEEE, 1996. p. 215-218.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Suyama, T, Sawada, H & Nagoya, A 1996, LUT-based FPGA technology mapping using permissible functions. in Proceedings of the IEEE International Conference on VLSI Design. IEEE, pp. 215-218, Proceedings of the 1996 9th International Conference on VLSI Design, Bangalore, India, 1/3/96.
Suyama T, Sawada H, Nagoya A. LUT-based FPGA technology mapping using permissible functions. In Proceedings of the IEEE International Conference on VLSI Design. IEEE. 1996. p. 215-218
Suyama, Takayuki ; Sawada, Hiroshi ; Nagoya, Akira. / LUT-based FPGA technology mapping using permissible functions. Proceedings of the IEEE International Conference on VLSI Design. IEEE, 1996. pp. 215-218
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