Logic synthesis for look-up table based fpgas using functional decomposition and boolean resubstitution

Hiroshi Sawada, Takayuki Suyama, Akira Nagoya

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

This paper presents a logic synthesis method for look-up table (LUT) based field programmable gate arrays (FPGAs). We determine functions to be mapped to LUTs by functional decomposition for each of single-output functions. To share LUTs among several functions, we use a new Boolean resubstitution technique. Resubstitution is used to determine whether an existing function is useful to realize another function; thus, we can share common functions among two or more functions. The Boolean resubstitution proposed in this paper is customized for an LUT network synthesis because it is based on support minimization for an incompletely specified function. Experimental results show that our synthesis method produces a small size circuit in a practical amount of time.

Original languageEnglish
Pages (from-to)1017-1023
Number of pages7
JournalIEICE Transactions on Information and Systems
VolumeE80-D
Issue number10
Publication statusPublished - 1997
Externally publishedYes

Fingerprint

Decomposition
Logic Synthesis
Field programmable gate arrays (FPGA)
Networks (circuits)

Keywords

  • Boolean resubstitution
  • FPGA
  • Functional decomposition
  • Look-up table (LUT)
  • Support minimization

ASJC Scopus subject areas

  • Information Systems
  • Computer Graphics and Computer-Aided Design
  • Software

Cite this

Logic synthesis for look-up table based fpgas using functional decomposition and boolean resubstitution. / Sawada, Hiroshi; Suyama, Takayuki; Nagoya, Akira.

In: IEICE Transactions on Information and Systems, Vol. E80-D, No. 10, 1997, p. 1017-1023.

Research output: Contribution to journalArticle

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