Logic synthesis for look-up table based FPGAs using functional decomposition and support minimization

Hiroshi Sawada, Takayuki Suyama, Akira Nagoya

Research output: Chapter in Book/Report/Conference proceedingConference contribution

37 Citations (Scopus)

Abstract

This paper presents a logic synthesis method for look-up table (LUT) based field programmable gate arrays (FPGAs). We determine functions to be mapped to LUTs by functional decomposition. We use not only disjunctive decomposition but also nondisjunctive decomposition. Furthermore, we propose a new Boolean resubstitution technique customized for an LUT network synthesis. Resubstitution is used to determine whether an existing function is useful to realize another function; thus, we can share the common function among two or more functions. The Boolean resubstitution is effectively carried out by solving a support minimization problem for an incompletely specified function. We can also handle satisfiability don't cares of an LUT network using the technique.

Original languageEnglish
Title of host publicationIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
Editors Anon
PublisherIEEE
Pages353-358
Number of pages6
Publication statusPublished - 1995
Externally publishedYes
EventProceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design - San Jose, CA, USA
Duration: Nov 5 1995Nov 9 1995

Other

OtherProceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design
CitySan Jose, CA, USA
Period11/5/9511/9/95

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ASJC Scopus subject areas

  • Software

Cite this

Sawada, H., Suyama, T., & Nagoya, A. (1995). Logic synthesis for look-up table based FPGAs using functional decomposition and support minimization. In Anon (Ed.), IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers (pp. 353-358). IEEE.