Abstract
Among lithographic characteristics, line-edge roughness (LER) of resist patterns now assumes even greater importance than before. This is because the variation of device sizes due to LER cannot be neglected as device sizes shrink. Therefore, LER has to be reduced as much as possible in next-generation lithography. For LER reduction, it is essential to elucidate its cause based on precise evaluations. We have been working to develop methods for the measurement and analysis of LER and elucidate the cause of LER for an electron-beam chain-scission type of resist, which has a simple imaging mechanism. In this report, we describe two LER issues: its characterization and material origin.
Original language | English |
---|---|
Title of host publication | 2002 International Microprocesses and Nanotechnology Conference, MNC 2002 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 78-79 |
Number of pages | 2 |
ISBN (Print) | 4891140313, 9784891140311 |
DOIs | |
Publication status | Published - 2002 |
Externally published | Yes |
Event | International Microprocesses and Nanotechnology Conference, MNC 2002 - Tokyo, Japan Duration: Nov 6 2002 → Nov 8 2002 |
Other
Other | International Microprocesses and Nanotechnology Conference, MNC 2002 |
---|---|
Country/Territory | Japan |
City | Tokyo |
Period | 11/6/02 → 11/8/02 |
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering