Integrated approach for synthesizing LUT networks

Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a method for synthesizing look-up table (LUT) networks. The strategy employed by our method is very different from the strategies of previous methods; many decomposition methods that are not only algebraic but also functional are integrated very well. Our method can be thought of as a general framework for LUT network synthesis integrating various decomposition methods. The experimental results are very encouraging.

Original languageEnglish
Title of host publicationProceedings of the IEEE Great Lakes Symposium on VLSI
PublisherIEEE
Pages136-139
Number of pages4
ISBN (Print)0769501044
Publication statusPublished - Dec 1 1999
Externally publishedYes
EventProceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99) - Ann Arbor, MI, USA
Duration: Mar 4 1999Mar 6 1999

Publication series

NameProceedings of the IEEE Great Lakes Symposium on VLSI
ISSN (Print)1066-1395

Other

OtherProceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99)
CityAnn Arbor, MI, USA
Period3/4/993/6/99

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Yamashita, S., Sawada, H., & Nagoya, A. (1999). Integrated approach for synthesizing LUT networks. In Proceedings of the IEEE Great Lakes Symposium on VLSI (pp. 136-139). (Proceedings of the IEEE Great Lakes Symposium on VLSI). IEEE.