Insertion of parallel RL circuits into power distribution network for simultaneous switching current reduction and power integrity

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

We investigated a method using parallel RL circuits inserted into power distribution network (PDN) of integrated circuits (ICs) to enhance the IC in EMI and PI performance. Optimal damping resistances of the parallel RL circuit were derived from a characteristic equation of an equivalent circuit of a partial PDN that contributed to PDN resonances dominantly. The parallel RL circuit with the optimal resistances damps the PDN resonances as quickly as possible and reduces peaks in simultaneous switching current that will cause EMI and in input impedance of PDN related to PI. We validated the parallel RL circuit with respect to EMI and PI performance of ICs numerically and experimentally. Results of these validation showed that the proposed method descend the simultaneous switching current at both chip-package-board and on-board resonant frequency. It is also confirmed that insertion of the parallel RL circuits into the power trace reduced the impedance peak due to the chip-package-board resonance.

Original languageEnglish
Title of host publicationcccc2012 Asia-Pacific Symposium on Electromagnetic Compatibility, APEMC 2012 - Proceedings
Pages417-420
Number of pages4
DOIs
Publication statusPublished - 2012
Event2012 Asia-Pacific Symposium on Electromagnetic Compatibility, APEMC 2012 - Singapore, Singapore
Duration: May 21 2012May 24 2012

Other

Other2012 Asia-Pacific Symposium on Electromagnetic Compatibility, APEMC 2012
CountrySingapore
CitySingapore
Period5/21/125/24/12

Fingerprint

Electric power distribution
Networks (circuits)
Integrated circuits
Equivalent circuits
Natural frequencies
Damping

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Iokibe, K., Yano, Y., & Toyota, Y. (2012). Insertion of parallel RL circuits into power distribution network for simultaneous switching current reduction and power integrity. In cccc2012 Asia-Pacific Symposium on Electromagnetic Compatibility, APEMC 2012 - Proceedings (pp. 417-420). [6237943] https://doi.org/10.1109/APEMC.2012.6237943

Insertion of parallel RL circuits into power distribution network for simultaneous switching current reduction and power integrity. / Iokibe, Kengo; Yano, Yusuke; Toyota, Yoshitaka.

cccc2012 Asia-Pacific Symposium on Electromagnetic Compatibility, APEMC 2012 - Proceedings. 2012. p. 417-420 6237943.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Iokibe, K, Yano, Y & Toyota, Y 2012, Insertion of parallel RL circuits into power distribution network for simultaneous switching current reduction and power integrity. in cccc2012 Asia-Pacific Symposium on Electromagnetic Compatibility, APEMC 2012 - Proceedings., 6237943, pp. 417-420, 2012 Asia-Pacific Symposium on Electromagnetic Compatibility, APEMC 2012, Singapore, Singapore, 5/21/12. https://doi.org/10.1109/APEMC.2012.6237943
Iokibe K, Yano Y, Toyota Y. Insertion of parallel RL circuits into power distribution network for simultaneous switching current reduction and power integrity. In cccc2012 Asia-Pacific Symposium on Electromagnetic Compatibility, APEMC 2012 - Proceedings. 2012. p. 417-420. 6237943 https://doi.org/10.1109/APEMC.2012.6237943
Iokibe, Kengo ; Yano, Yusuke ; Toyota, Yoshitaka. / Insertion of parallel RL circuits into power distribution network for simultaneous switching current reduction and power integrity. cccc2012 Asia-Pacific Symposium on Electromagnetic Compatibility, APEMC 2012 - Proceedings. 2012. pp. 417-420
@inproceedings{26d9d0c6df924774aa62e754c3f6b673,
title = "Insertion of parallel RL circuits into power distribution network for simultaneous switching current reduction and power integrity",
abstract = "We investigated a method using parallel RL circuits inserted into power distribution network (PDN) of integrated circuits (ICs) to enhance the IC in EMI and PI performance. Optimal damping resistances of the parallel RL circuit were derived from a characteristic equation of an equivalent circuit of a partial PDN that contributed to PDN resonances dominantly. The parallel RL circuit with the optimal resistances damps the PDN resonances as quickly as possible and reduces peaks in simultaneous switching current that will cause EMI and in input impedance of PDN related to PI. We validated the parallel RL circuit with respect to EMI and PI performance of ICs numerically and experimentally. Results of these validation showed that the proposed method descend the simultaneous switching current at both chip-package-board and on-board resonant frequency. It is also confirmed that insertion of the parallel RL circuits into the power trace reduced the impedance peak due to the chip-package-board resonance.",
author = "Kengo Iokibe and Yusuke Yano and Yoshitaka Toyota",
year = "2012",
doi = "10.1109/APEMC.2012.6237943",
language = "English",
isbn = "9781457715587",
pages = "417--420",
booktitle = "cccc2012 Asia-Pacific Symposium on Electromagnetic Compatibility, APEMC 2012 - Proceedings",

}

TY - GEN

T1 - Insertion of parallel RL circuits into power distribution network for simultaneous switching current reduction and power integrity

AU - Iokibe, Kengo

AU - Yano, Yusuke

AU - Toyota, Yoshitaka

PY - 2012

Y1 - 2012

N2 - We investigated a method using parallel RL circuits inserted into power distribution network (PDN) of integrated circuits (ICs) to enhance the IC in EMI and PI performance. Optimal damping resistances of the parallel RL circuit were derived from a characteristic equation of an equivalent circuit of a partial PDN that contributed to PDN resonances dominantly. The parallel RL circuit with the optimal resistances damps the PDN resonances as quickly as possible and reduces peaks in simultaneous switching current that will cause EMI and in input impedance of PDN related to PI. We validated the parallel RL circuit with respect to EMI and PI performance of ICs numerically and experimentally. Results of these validation showed that the proposed method descend the simultaneous switching current at both chip-package-board and on-board resonant frequency. It is also confirmed that insertion of the parallel RL circuits into the power trace reduced the impedance peak due to the chip-package-board resonance.

AB - We investigated a method using parallel RL circuits inserted into power distribution network (PDN) of integrated circuits (ICs) to enhance the IC in EMI and PI performance. Optimal damping resistances of the parallel RL circuit were derived from a characteristic equation of an equivalent circuit of a partial PDN that contributed to PDN resonances dominantly. The parallel RL circuit with the optimal resistances damps the PDN resonances as quickly as possible and reduces peaks in simultaneous switching current that will cause EMI and in input impedance of PDN related to PI. We validated the parallel RL circuit with respect to EMI and PI performance of ICs numerically and experimentally. Results of these validation showed that the proposed method descend the simultaneous switching current at both chip-package-board and on-board resonant frequency. It is also confirmed that insertion of the parallel RL circuits into the power trace reduced the impedance peak due to the chip-package-board resonance.

UR - http://www.scopus.com/inward/record.url?scp=84864858795&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84864858795&partnerID=8YFLogxK

U2 - 10.1109/APEMC.2012.6237943

DO - 10.1109/APEMC.2012.6237943

M3 - Conference contribution

SN - 9781457715587

SP - 417

EP - 420

BT - cccc2012 Asia-Pacific Symposium on Electromagnetic Compatibility, APEMC 2012 - Proceedings

ER -