Improvement of linear equivalent circuit model to identify simultaneous switching noise current in cryptographic integrated circuits

Kengo Iokibe, Tetsuo Amano, Kaoru Okamoto, Yoshitaka Toyota, Tetsushi Watanabe

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

The authors previously proposed a method based on a linear equivalent circuit model to predict vulnerability of cryptographic devices before fabrication. The method was verified to demonstrate the correlation power analysis attack, a major side-channel attack method, to a cryptographic device with outstanding accuracy. However, no obvious correlation was seen between the equivalent current source modeling the generation of the simultaneous switching noise (SSN) current in the circuit model and the encryption operation used in the previous study. Therefore, in this study, we improved the topology of the linear equivalent circuit model matched with the physical construction of the power distribution network (PDN) and re-identified the equivalent current source. By comparing the improved current source with the encryption operation, obvious correlations between them were found with respect to the period of the round operation and the dependency of the SSN current on the Hamming distance between successive intermediates. The improved equivalent current source was applied on a Field-Programmable Gate Array (FPGA) in which an Advance Encryption Standard (AES) circuit was implemented to simulate power traces that were confirmed to coincide with measured ones. Correlation between the simulated power traces and the power model was investigated using a set of 1000 plaintexts. As a result, the correlation coefficients agreed well with those for measured power traces. Improving the equivalent circuit model topology, thus, helped to identify the SSN current generated in the FPGA during the AES operation.

Original languageEnglish
Title of host publicationIEEE International Symposium on Electromagnetic Compatibility
Pages834-839
Number of pages6
DOIs
Publication statusPublished - 2013
Event2013 IEEE International Symposium on Electromagnetic Compatibility, EMC 2013 - Denver, CO, United States
Duration: Aug 5 2013Aug 9 2013

Other

Other2013 IEEE International Symposium on Electromagnetic Compatibility, EMC 2013
CountryUnited States
CityDenver, CO
Period8/5/138/9/13

Fingerprint

linear circuits
equivalent circuits
Equivalent circuits
integrated circuits
Integrated circuits
Cryptography
Field programmable gate arrays (FPGA)
field-programmable gate arrays
Topology
attack
Hamming distance
Networks (circuits)
topology
Electric power distribution
vulnerability
correlation coefficients
Fabrication
fabrication

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Condensed Matter Physics

Cite this

Iokibe, K., Amano, T., Okamoto, K., Toyota, Y., & Watanabe, T. (2013). Improvement of linear equivalent circuit model to identify simultaneous switching noise current in cryptographic integrated circuits. In IEEE International Symposium on Electromagnetic Compatibility (pp. 834-839). [6670526] https://doi.org/10.1109/ISEMC.2013.6670526

Improvement of linear equivalent circuit model to identify simultaneous switching noise current in cryptographic integrated circuits. / Iokibe, Kengo; Amano, Tetsuo; Okamoto, Kaoru; Toyota, Yoshitaka; Watanabe, Tetsushi.

IEEE International Symposium on Electromagnetic Compatibility. 2013. p. 834-839 6670526.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Iokibe, K, Amano, T, Okamoto, K, Toyota, Y & Watanabe, T 2013, Improvement of linear equivalent circuit model to identify simultaneous switching noise current in cryptographic integrated circuits. in IEEE International Symposium on Electromagnetic Compatibility., 6670526, pp. 834-839, 2013 IEEE International Symposium on Electromagnetic Compatibility, EMC 2013, Denver, CO, United States, 8/5/13. https://doi.org/10.1109/ISEMC.2013.6670526
Iokibe K, Amano T, Okamoto K, Toyota Y, Watanabe T. Improvement of linear equivalent circuit model to identify simultaneous switching noise current in cryptographic integrated circuits. In IEEE International Symposium on Electromagnetic Compatibility. 2013. p. 834-839. 6670526 https://doi.org/10.1109/ISEMC.2013.6670526
Iokibe, Kengo ; Amano, Tetsuo ; Okamoto, Kaoru ; Toyota, Yoshitaka ; Watanabe, Tetsushi. / Improvement of linear equivalent circuit model to identify simultaneous switching noise current in cryptographic integrated circuits. IEEE International Symposium on Electromagnetic Compatibility. 2013. pp. 834-839
@inproceedings{4bd1717f4e8c4b679116278ecf5e4a0f,
title = "Improvement of linear equivalent circuit model to identify simultaneous switching noise current in cryptographic integrated circuits",
abstract = "The authors previously proposed a method based on a linear equivalent circuit model to predict vulnerability of cryptographic devices before fabrication. The method was verified to demonstrate the correlation power analysis attack, a major side-channel attack method, to a cryptographic device with outstanding accuracy. However, no obvious correlation was seen between the equivalent current source modeling the generation of the simultaneous switching noise (SSN) current in the circuit model and the encryption operation used in the previous study. Therefore, in this study, we improved the topology of the linear equivalent circuit model matched with the physical construction of the power distribution network (PDN) and re-identified the equivalent current source. By comparing the improved current source with the encryption operation, obvious correlations between them were found with respect to the period of the round operation and the dependency of the SSN current on the Hamming distance between successive intermediates. The improved equivalent current source was applied on a Field-Programmable Gate Array (FPGA) in which an Advance Encryption Standard (AES) circuit was implemented to simulate power traces that were confirmed to coincide with measured ones. Correlation between the simulated power traces and the power model was investigated using a set of 1000 plaintexts. As a result, the correlation coefficients agreed well with those for measured power traces. Improving the equivalent circuit model topology, thus, helped to identify the SSN current generated in the FPGA during the AES operation.",
author = "Kengo Iokibe and Tetsuo Amano and Kaoru Okamoto and Yoshitaka Toyota and Tetsushi Watanabe",
year = "2013",
doi = "10.1109/ISEMC.2013.6670526",
language = "English",
isbn = "9781479904082",
pages = "834--839",
booktitle = "IEEE International Symposium on Electromagnetic Compatibility",

}

TY - GEN

T1 - Improvement of linear equivalent circuit model to identify simultaneous switching noise current in cryptographic integrated circuits

AU - Iokibe, Kengo

AU - Amano, Tetsuo

AU - Okamoto, Kaoru

AU - Toyota, Yoshitaka

AU - Watanabe, Tetsushi

PY - 2013

Y1 - 2013

N2 - The authors previously proposed a method based on a linear equivalent circuit model to predict vulnerability of cryptographic devices before fabrication. The method was verified to demonstrate the correlation power analysis attack, a major side-channel attack method, to a cryptographic device with outstanding accuracy. However, no obvious correlation was seen between the equivalent current source modeling the generation of the simultaneous switching noise (SSN) current in the circuit model and the encryption operation used in the previous study. Therefore, in this study, we improved the topology of the linear equivalent circuit model matched with the physical construction of the power distribution network (PDN) and re-identified the equivalent current source. By comparing the improved current source with the encryption operation, obvious correlations between them were found with respect to the period of the round operation and the dependency of the SSN current on the Hamming distance between successive intermediates. The improved equivalent current source was applied on a Field-Programmable Gate Array (FPGA) in which an Advance Encryption Standard (AES) circuit was implemented to simulate power traces that were confirmed to coincide with measured ones. Correlation between the simulated power traces and the power model was investigated using a set of 1000 plaintexts. As a result, the correlation coefficients agreed well with those for measured power traces. Improving the equivalent circuit model topology, thus, helped to identify the SSN current generated in the FPGA during the AES operation.

AB - The authors previously proposed a method based on a linear equivalent circuit model to predict vulnerability of cryptographic devices before fabrication. The method was verified to demonstrate the correlation power analysis attack, a major side-channel attack method, to a cryptographic device with outstanding accuracy. However, no obvious correlation was seen between the equivalent current source modeling the generation of the simultaneous switching noise (SSN) current in the circuit model and the encryption operation used in the previous study. Therefore, in this study, we improved the topology of the linear equivalent circuit model matched with the physical construction of the power distribution network (PDN) and re-identified the equivalent current source. By comparing the improved current source with the encryption operation, obvious correlations between them were found with respect to the period of the round operation and the dependency of the SSN current on the Hamming distance between successive intermediates. The improved equivalent current source was applied on a Field-Programmable Gate Array (FPGA) in which an Advance Encryption Standard (AES) circuit was implemented to simulate power traces that were confirmed to coincide with measured ones. Correlation between the simulated power traces and the power model was investigated using a set of 1000 plaintexts. As a result, the correlation coefficients agreed well with those for measured power traces. Improving the equivalent circuit model topology, thus, helped to identify the SSN current generated in the FPGA during the AES operation.

UR - http://www.scopus.com/inward/record.url?scp=84893203470&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84893203470&partnerID=8YFLogxK

U2 - 10.1109/ISEMC.2013.6670526

DO - 10.1109/ISEMC.2013.6670526

M3 - Conference contribution

SN - 9781479904082

SP - 834

EP - 839

BT - IEEE International Symposium on Electromagnetic Compatibility

ER -