TY - JOUR
T1 - Hybrid Montgomery reduction
AU - Seo, Hwajeong
AU - Liu, Zhe
AU - Nogami, Yasuyuki
AU - Choi, Jongseok
AU - Kim, Howon
N1 - Funding Information:
This research was partly supported by the MSIP (Ministry of Science, ICT and Future Planning), Korea, under the ITRC (Information Technology Research Center) support program (IITP-2016-H8501-16-1017) supervised by the IITP (Institute for Information and communications Technology Promotion) and partly supported by Institute for Information and communications Technology Promotion (IITP) grant funded by the Korea government (MSIP) (No. 10043907, Development of high performance IoT device and Open Platform with Intelligent Software).
Publisher Copyright:
© 2016 ACM.
PY - 2016/5
Y1 - 2016/5
N2 - In this article, we present a hybrid method to improve the performance of the Montgomery reduction by taking advantage of the Karatsuba technique. We divide the Montgomery reduction into two sub-parts, including one for the conventional Montgomery reduction and the other one for Karatsuba-aided multiplication. This approach reduces the multiplication complexity of n-limb Montgomery reduction from θ(n2 + n) to asymptotic complexity θ(7n2/8 + n). Our practical implementation results over an 8-bit microcontroller also show performance enhancements by 11%.
AB - In this article, we present a hybrid method to improve the performance of the Montgomery reduction by taking advantage of the Karatsuba technique. We divide the Montgomery reduction into two sub-parts, including one for the conventional Montgomery reduction and the other one for Karatsuba-aided multiplication. This approach reduces the multiplication complexity of n-limb Montgomery reduction from θ(n2 + n) to asymptotic complexity θ(7n2/8 + n). Our practical implementation results over an 8-bit microcontroller also show performance enhancements by 11%.
KW - Karatsuba multiplication
KW - Montgomery reduction
KW - Public key cryptography
KW - Software implementation
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U2 - 10.1145/2890502
DO - 10.1145/2890502
M3 - Article
AN - SCOPUS:84974559415
VL - 15
JO - Transactions on Embedded Computing Systems
JF - Transactions on Embedded Computing Systems
SN - 1539-9087
IS - 3
M1 - 58
ER -