Holographic memory calculation FPGA accelerator for optically reconfigurable gate arrays

Takumi Fujimori, Minoru Watanabe

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Recently, radiation-hardened optically reconfigurable gate arrays have been developed for space applications. An optically reconfigurable gate array comprises a holographic memory, a laser array, and an optically reconfigurable gate array VLSI. Since the optically reconfigurable gate array is a type of multi-context field programmable gate array (FPGA), several configuration contexts must be implemented onto the holographic memory on an optically reconfigurable gate array. However, the holographic memory pattern calculation is a heavy operation in addition to logic synthesis and to place and route operations. This paper therefore presents an FPGA hardware accelerator for hologram memory calculation for optically reconfigurable gate arrays with an FPGA (Cyclone V; Altera Corp.).Performance evaluation results show that the calculation speed of a hologram memory pattern including 512 bright bits is 16.9 times higher than multi-thread calculation on the CPU (Core i7-4770; Intel Corp.). Furthermore, the FPGA hardware accelerator power consumption is only 6 W, compared to 95 W of the CPU (Core i7-4770; Intel Corp.).

Original languageEnglish
Title of host publicationProceedings - 2017 IEEE 15th International Conference on Dependable, Autonomic and Secure Computing, 2017 IEEE 15th International Conference on Pervasive Intelligence and Computing, 2017 IEEE 3rd International Conference on Big Data Intelligence and Computing and 2017 IEEE Cyber Science and Technology Congress, DASC-PICom-DataCom-CyberSciTec 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages620-625
Number of pages6
ISBN (Electronic)9781538619551
DOIs
Publication statusPublished - Mar 29 2018
Externally publishedYes
Event15th IEEE International Conference on Dependable, Autonomic and Secure Computing, 2017 IEEE 15th International Conference on Pervasive Intelligence and Computing, 2017 IEEE 3rd International Conference on Big Data Intelligence and Computing and 2017 IEEE Cyber Science and Technology Congress, DASC-PICom-DataCom-CyberSciTec 2017 - Orlando, United States
Duration: Nov 6 2017Nov 11 2017

Publication series

NameProceedings - 2017 IEEE 15th International Conference on Dependable, Autonomic and Secure Computing, 2017 IEEE 15th International Conference on Pervasive Intelligence and Computing, 2017 IEEE 3rd International Conference on Big Data Intelligence and Computing and 2017 IEEE Cyber Science and Technology Congress, DASC-PICom-DataCom-CyberSciTec 2017
Volume2018-January

Conference

Conference15th IEEE International Conference on Dependable, Autonomic and Secure Computing, 2017 IEEE 15th International Conference on Pervasive Intelligence and Computing, 2017 IEEE 3rd International Conference on Big Data Intelligence and Computing and 2017 IEEE Cyber Science and Technology Congress, DASC-PICom-DataCom-CyberSciTec 2017
Country/TerritoryUnited States
CityOrlando
Period11/6/1711/11/17

Keywords

  • Field programmable gate array
  • Optically reconfigurable gate array

ASJC Scopus subject areas

  • Safety, Risk, Reliability and Quality
  • Health Informatics
  • Artificial Intelligence
  • Computer Networks and Communications
  • Hardware and Architecture
  • Computer Science Applications
  • Information Systems

Fingerprint

Dive into the research topics of 'Holographic memory calculation FPGA accelerator for optically reconfigurable gate arrays'. Together they form a unique fingerprint.

Cite this