This paper proposes a compact and highly efficient GF(2 8) inversion circuit design based on a combination of non-redundant and redundant Galois field (GF) (or finite field) arithmetic. The proposed design utilizes an optimal normal basis and redundant GF representations, called polynomial ring representation and redundantly represented basis, to implement GF(2 8) inversion using a tower field GF((24)2). The flexibility of the redundant representations provides efficient mappings from/to the GF(2 8). This paper evaluates the efficacy of the proposed circuit by gate counts and logic synthesis with a 65-nm CMOS standard cell library in comparison with conventional circuits. Consequently, we show that the proposed circuit achieves approximately 25% higher area–time efficiency than the conventional best inversion circuit in our environment. We also demonstrate that AES S-Box with the proposed circuit achieves the best area–time efficiency.
- GF(2 ) inversion circuit
- Hardware implementation
ASJC Scopus subject areas
- Computer Networks and Communications