Hardware/software codesign method for a general purpose reconfigurable co-processor

Shinji Kimura, Mitsuteru Yukishita, Yasufumi Itou, Akira Nagoya, Makoto Hirao, Katumasa Watanabe

Research output: Contribution to conferencePaper

2 Citations (Scopus)

Abstract

This paper shows a hardware/software codesign method for a computer system with a reconfigurable co-processor. The reconfigurable co-processor is constructed from FPGA's, internal cache and a control part, and is connected to the system bus of the computer system. This paper shows the architecture of the reconfigurable co-processor, a hardware/software separation method and a co-operation method via the DMA based memory sharing. We also show cooperation examples and the effectiveness of our approach for the fast execution of user processes.

Original languageEnglish
Pages147-151
Number of pages5
Publication statusPublished - Jan 1 1997
Externally publishedYes
EventProceedings of the 1997 5th International Workshop on Hardware/Software Codesign, CODES/CASHE'97 - Braunschweig, Ger
Duration: Mar 24 1997Mar 26 1997

Other

OtherProceedings of the 1997 5th International Workshop on Hardware/Software Codesign, CODES/CASHE'97
CityBraunschweig, Ger
Period3/24/973/26/97

ASJC Scopus subject areas

  • Hardware and Architecture

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  • Cite this

    Kimura, S., Yukishita, M., Itou, Y., Nagoya, A., Hirao, M., & Watanabe, K. (1997). Hardware/software codesign method for a general purpose reconfigurable co-processor. 147-151. Paper presented at Proceedings of the 1997 5th International Workshop on Hardware/Software Codesign, CODES/CASHE'97, Braunschweig, Ger, .