Full adder operation based on Si nanodot array device

Takuya Kaizawa; Masashi Arita; Akira Fujiwara; Kenji Yamazaki; Yukinori Ono; Hiroshi Inokawa; Yasuo Takahashi

doi:10.1109/SNW.2008.5418457

Full adder operation based on Si nanodot array device

Takuya Kaizawa, Masashi Arita, Akira Fujiwara, Kenji Yamazaki, Yukinori Ono, Hiroshi Inokawa, Yasuo Takahashi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

We demonstrate a highly functional Si-nanodot-array device that has three input gates and two output terminals. The device was fabricated on an SOI wafer using Si MOS processes. We confirmed that a single device can operate as both a half adder and a full adder when we carefully select the operation voltages.

Original language	English
Title of host publication	IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008
DOIs	https://doi.org/10.1109/SNW.2008.5418457
Publication status	Published - 2008
Externally published	Yes
Event	IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008 - Honolulu, HI, United States Duration: Jun 15 2008 → Jun 16 2008

Other

Other	IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008
Country	United States
City	Honolulu, HI
Period	6/15/08 → 6/16/08

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ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

Kaizawa, T., Arita, M., Fujiwara, A., Yamazaki, K., Ono, Y., Inokawa, H., & Takahashi, Y. (2008). Full adder operation based on Si nanodot array device. In IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008 [5418457] https://doi.org/10.1109/SNW.2008.5418457

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title = "Full adder operation based on Si nanodot array device",

abstract = "We demonstrate a highly functional Si-nanodot-array device that has three input gates and two output terminals. The device was fabricated on an SOI wafer using Si MOS processes. We confirmed that a single device can operate as both a half adder and a full adder when we carefully select the operation voltages.",

author = "Takuya Kaizawa and Masashi Arita and Akira Fujiwara and Kenji Yamazaki and Yukinori Ono and Hiroshi Inokawa and Yasuo Takahashi",

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doi = "10.1109/SNW.2008.5418457",

language = "English",

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AU - Kaizawa, Takuya

AU - Arita, Masashi

AU - Fujiwara, Akira

AU - Yamazaki, Kenji

AU - Ono, Yukinori

AU - Inokawa, Hiroshi

AU - Takahashi, Yasuo

PY - 2008

Y1 - 2008

N2 - We demonstrate a highly functional Si-nanodot-array device that has three input gates and two output terminals. The device was fabricated on an SOI wafer using Si MOS processes. We confirmed that a single device can operate as both a half adder and a full adder when we carefully select the operation voltages.

AB - We demonstrate a highly functional Si-nanodot-array device that has three input gates and two output terminals. The device was fabricated on an SOI wafer using Si MOS processes. We confirmed that a single device can operate as both a half adder and a full adder when we carefully select the operation voltages.

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U2 - 10.1109/SNW.2008.5418457

DO - 10.1109/SNW.2008.5418457

M3 - Conference contribution

AN - SCOPUS:77949997129

SN - 9781424420711

BT - IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008

T2 - IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008

Y2 - 15 June 2008 through 16 June 2008

ER -

Access to Document

10.1109/SNW.2008.5418457