Full adder operation based on Si nanodot array device

Takuya Kaizawa, Masashi Arita, Akira Fujiwara, Kenji Yamazaki, Yukinori Ono, Hiroshi Inokawa, Yasuo Takahashi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We demonstrate a highly functional Si-nanodot-array device that has three input gates and two output terminals. The device was fabricated on an SOI wafer using Si MOS processes. We confirmed that a single device can operate as both a half adder and a full adder when we carefully select the operation voltages.

Original languageEnglish
Title of host publicationIEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008
DOIs
Publication statusPublished - 2008
Externally publishedYes
EventIEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008 - Honolulu, HI, United States
Duration: Jun 15 2008Jun 16 2008

Other

OtherIEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008
CountryUnited States
CityHonolulu, HI
Period6/15/086/16/08

Fingerprint

Adders
Electric potential

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Kaizawa, T., Arita, M., Fujiwara, A., Yamazaki, K., Ono, Y., Inokawa, H., & Takahashi, Y. (2008). Full adder operation based on Si nanodot array device. In IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008 [5418457] https://doi.org/10.1109/SNW.2008.5418457

Full adder operation based on Si nanodot array device. / Kaizawa, Takuya; Arita, Masashi; Fujiwara, Akira; Yamazaki, Kenji; Ono, Yukinori; Inokawa, Hiroshi; Takahashi, Yasuo.

IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008. 2008. 5418457.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kaizawa, T, Arita, M, Fujiwara, A, Yamazaki, K, Ono, Y, Inokawa, H & Takahashi, Y 2008, Full adder operation based on Si nanodot array device. in IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008., 5418457, IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008, Honolulu, HI, United States, 6/15/08. https://doi.org/10.1109/SNW.2008.5418457
Kaizawa T, Arita M, Fujiwara A, Yamazaki K, Ono Y, Inokawa H et al. Full adder operation based on Si nanodot array device. In IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008. 2008. 5418457 https://doi.org/10.1109/SNW.2008.5418457
Kaizawa, Takuya ; Arita, Masashi ; Fujiwara, Akira ; Yamazaki, Kenji ; Ono, Yukinori ; Inokawa, Hiroshi ; Takahashi, Yasuo. / Full adder operation based on Si nanodot array device. IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008. 2008.
@inproceedings{2a4fa2c625e2423894826768d9157921,
title = "Full adder operation based on Si nanodot array device",
abstract = "We demonstrate a highly functional Si-nanodot-array device that has three input gates and two output terminals. The device was fabricated on an SOI wafer using Si MOS processes. We confirmed that a single device can operate as both a half adder and a full adder when we carefully select the operation voltages.",
author = "Takuya Kaizawa and Masashi Arita and Akira Fujiwara and Kenji Yamazaki and Yukinori Ono and Hiroshi Inokawa and Yasuo Takahashi",
year = "2008",
doi = "10.1109/SNW.2008.5418457",
language = "English",
isbn = "9781424420711",
booktitle = "IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008",

}

TY - GEN

T1 - Full adder operation based on Si nanodot array device

AU - Kaizawa, Takuya

AU - Arita, Masashi

AU - Fujiwara, Akira

AU - Yamazaki, Kenji

AU - Ono, Yukinori

AU - Inokawa, Hiroshi

AU - Takahashi, Yasuo

PY - 2008

Y1 - 2008

N2 - We demonstrate a highly functional Si-nanodot-array device that has three input gates and two output terminals. The device was fabricated on an SOI wafer using Si MOS processes. We confirmed that a single device can operate as both a half adder and a full adder when we carefully select the operation voltages.

AB - We demonstrate a highly functional Si-nanodot-array device that has three input gates and two output terminals. The device was fabricated on an SOI wafer using Si MOS processes. We confirmed that a single device can operate as both a half adder and a full adder when we carefully select the operation voltages.

UR - http://www.scopus.com/inward/record.url?scp=77949997129&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77949997129&partnerID=8YFLogxK

U2 - 10.1109/SNW.2008.5418457

DO - 10.1109/SNW.2008.5418457

M3 - Conference contribution

SN - 9781424420711

BT - IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008

ER -