TY - GEN
T1 - Full adder operation based on Si nanodot array device
AU - Kaizawa, Takuya
AU - Arita, Masashi
AU - Fujiwara, Akira
AU - Yamazaki, Kenji
AU - Ono, Yukinori
AU - Inokawa, Hiroshi
AU - Takahashi, Yasuo
PY - 2008/12/1
Y1 - 2008/12/1
N2 - We demonstrate a highly functional Si-nanodot-array device that has three input gates and two output terminals. The device was fabricated on an SOI wafer using Si MOS processes. We confirmed that a single device can operate as both a half adder and a full adder when we carefully select the operation voltages.
AB - We demonstrate a highly functional Si-nanodot-array device that has three input gates and two output terminals. The device was fabricated on an SOI wafer using Si MOS processes. We confirmed that a single device can operate as both a half adder and a full adder when we carefully select the operation voltages.
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U2 - 10.1109/SNW.2008.5418457
DO - 10.1109/SNW.2008.5418457
M3 - Conference contribution
AN - SCOPUS:77949997129
SN - 9781424420711
T3 - IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008
BT - IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008
T2 - IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008
Y2 - 15 June 2008 through 16 June 2008
ER -