Full adder operation based on Si nanodot array device

Takuya Kaizawa, Masashi Arita, Akira Fujiwara, Kenji Yamazaki, Yukinori Ono, Hiroshi Inokawa, Yasuo Takahashi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We demonstrate a highly functional Si-nanodot-array device that has three input gates and two output terminals. The device was fabricated on an SOI wafer using Si MOS processes. We confirmed that a single device can operate as both a half adder and a full adder when we carefully select the operation voltages.

Original languageEnglish
Title of host publicationIEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008
DOIs
Publication statusPublished - Dec 1 2008
EventIEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008 - Honolulu, HI, United States
Duration: Jun 15 2008Jun 16 2008

Publication series

NameIEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008

Other

OtherIEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008
CountryUnited States
CityHonolulu, HI
Period6/15/086/16/08

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Kaizawa, T., Arita, M., Fujiwara, A., Yamazaki, K., Ono, Y., Inokawa, H., & Takahashi, Y. (2008). Full adder operation based on Si nanodot array device. In IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008 [5418457] (IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008). https://doi.org/10.1109/SNW.2008.5418457