Abstract
We demonstrate a highly functional Si-nanodot-array device that has three input gates and two output terminals. The device was fabricated on an SOI wafer using Si MOS processes. We confirmed that a single device can operate as both a half adder and a full adder when we carefully select the operation voltages.
| Original language | English |
|---|---|
| Title of host publication | IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008 |
| DOIs | |
| Publication status | Published - 2008 |
| Externally published | Yes |
| Event | IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008 - Honolulu, HI, United States Duration: Jun 15 2008 → Jun 16 2008 |
Other
| Other | IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008 |
|---|---|
| Country | United States |
| City | Honolulu, HI |
| Period | 6/15/08 → 6/16/08 |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
Full adder operation based on Si nanodot array device. / Kaizawa, Takuya; Arita, Masashi; Fujiwara, Akira; Yamazaki, Kenji; Ono, Yukinori; Inokawa, Hiroshi; Takahashi, Yasuo.
IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008. 2008. 5418457.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Full adder operation based on Si nanodot array device
AU - Kaizawa, Takuya
AU - Arita, Masashi
AU - Fujiwara, Akira
AU - Yamazaki, Kenji
AU - Ono, Yukinori
AU - Inokawa, Hiroshi
AU - Takahashi, Yasuo
PY - 2008
Y1 - 2008
N2 - We demonstrate a highly functional Si-nanodot-array device that has three input gates and two output terminals. The device was fabricated on an SOI wafer using Si MOS processes. We confirmed that a single device can operate as both a half adder and a full adder when we carefully select the operation voltages.
AB - We demonstrate a highly functional Si-nanodot-array device that has three input gates and two output terminals. The device was fabricated on an SOI wafer using Si MOS processes. We confirmed that a single device can operate as both a half adder and a full adder when we carefully select the operation voltages.
UR - http://www.scopus.com/inward/record.url?scp=77949997129&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77949997129&partnerID=8YFLogxK
U2 - 10.1109/SNW.2008.5418457
DO - 10.1109/SNW.2008.5418457
M3 - Conference contribution
SN - 9781424420711
BT - IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008
ER -