FPGA Blokus Duo Solver using a massively parallel architecture

Takashi Yoza; Retsu Moriwaki; Yuki Torigai; Yuki Kamikubo; Takayuki Kubota; Takahiro Watanabe; Takumi Fujimori; Hiroyuki Ito; Masato Seo; Kouta Akagi; Yuichiro Yamaji; Minoru Watanabe

doi:10.1109/FPT.2013.6718426

FPGA Blokus Duo Solver using a massively parallel architecture

Takashi Yoza, Retsu Moriwaki, Yuki Torigai, Yuki Kamikubo, Takayuki Kubota, Takahiro Watanabe, Takumi Fujimori, Hiroyuki Ito, Masato Seo, Kouta Akagi, Yuichiro Yamaji, Minoru Watanabe

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Citations (Scopus)

Abstract

Recently, many game programs have been developed aggressively as hardware on field programmable gate arrays (FPGAs) because of the extremely large solution space of such games as the Connecta game, Blokus Duo game, and others so that the computational capabilities of computers are currently insufficient to search all possible solutions. This report describes an FPGA acceleration experiment for the Blokus Duo game. The FPGA Blokus Duo Solver was implemented on an Arria Π GX FPGA (Altera Corp.). Its operation speed is 25 times faster than C++ based software operation of the same algorithm on a Core i7 processor.

Original language	English
Title of host publication	FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology
Pages	494-497
Number of pages	4
DOIs	https://doi.org/10.1109/FPT.2013.6718426
Publication status	Published - 2013
Externally published	Yes
Event	2013 12th International Conference on Field-Programmable Technology, FPT 2013 - Kyoto, Japan Duration: Dec 9 2013 → Dec 11 2013

Publication series

Name	FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology

Conference

Conference	2013 12th International Conference on Field-Programmable Technology, FPT 2013
Country/Territory	Japan
City	Kyoto
Period	12/9/13 → 12/11/13

ASJC Scopus subject areas

Software

Access to Document

10.1109/FPT.2013.6718426

Cite this

Yoza, T., Moriwaki, R., Torigai, Y., Kamikubo, Y., Kubota, T., Watanabe, T., Fujimori, T., Ito, H., Seo, M., Akagi, K., Yamaji, Y., & Watanabe, M. (2013). FPGA Blokus Duo Solver using a massively parallel architecture. In FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology (pp. 494-497). [6718426] (FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology). https://doi.org/10.1109/FPT.2013.6718426

FPGA Blokus Duo Solver using a massively parallel architecture. / Yoza, Takashi; Moriwaki, Retsu; Torigai, Yuki et al.

FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology. 2013. p. 494-497 6718426 (FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Yoza, T, Moriwaki, R, Torigai, Y, Kamikubo, Y, Kubota, T, Watanabe, T, Fujimori, T, Ito, H, Seo, M, Akagi, K, Yamaji, Y & Watanabe, M 2013, FPGA Blokus Duo Solver using a massively parallel architecture. in FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology., 6718426, FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology, pp. 494-497, 2013 12th International Conference on Field-Programmable Technology, FPT 2013, Kyoto, Japan, 12/9/13. https://doi.org/10.1109/FPT.2013.6718426

Yoza T, Moriwaki R, Torigai Y, Kamikubo Y, Kubota T, Watanabe T et al. FPGA Blokus Duo Solver using a massively parallel architecture. In FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology. 2013. p. 494-497. 6718426. (FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology). doi: 10.1109/FPT.2013.6718426

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FPGA Blokus Duo Solver using a massively parallel architecture

Abstract

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Conference

ASJC Scopus subject areas

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