Formal verification method for combinatorial circuits at high level design

Research output: Contribution to journalArticle

Original languageEnglish
Pages (from-to)319-322
Number of pages4
JournalProc. of Asia and South Pacific Design Automation Conference
Publication statusPublished - 1999

Cite this

@article{10bd65e43438445a9d0911b5c6f34ce7,
title = "Formal verification method for combinatorial circuits at high level design",
author = "Nobuo Funabiki",
year = "1999",
language = "English",
pages = "319--322",
journal = "Proc. of Asia and South Pacific Design Automation Conference",

}

TY - JOUR

T1 - Formal verification method for combinatorial circuits at high level design

AU - Funabiki, Nobuo

PY - 1999

Y1 - 1999

M3 - Article

SP - 319

EP - 322

JO - Proc. of Asia and South Pacific Design Automation Conference

JF - Proc. of Asia and South Pacific Design Automation Conference

ER -