Gallium-nitride-field-effect transistors (GaN-FETs) are expected as a key component to the power density improvement of switching power converter for electric vehicles (EVs) because of their low on-resistance and fast switching capability. It is well known that the switching loss is influenced by the drain inductance, which is the parasitic inductance of the power loop, and can be minimized in principle by an appropriate design of the drain inductance. However, in switching power converters using Si-based power devices such as the Si-MOSFET and the Si-IGBT, it is usually difficult to design the drain inductance so that the switching loss minimizes because an appropriate drain inductance becomes too large, thus resulting in large surge voltages of the switching device. On the other hand, this may not be the case when using the GaN-FETs because the inductance that can minimize the switching loss may become small due to the high-di/dt switching. Therefore, the purpose of this study is to show the feasibility of the parasitic drain inductance design that the switching loss of the GaN-FET in the bridge circuit can be minimized while keeping the surge voltage of the GaN-FET within acceptable limits. The appropriateness of this insight is verified by simulation.