Fast method for timing verification that uses the conditions that cause changes in the output values of gates

Atsushi Ohnishi, Yuji Sugiyama

Research output: Contribution to journalArticle

Abstract

This paper discusses a fast method for timing verification which uses the conditions that cause changes in the output value of gates in a combinational logic circuit. The methods proposed previously derive the conditions that make a circuit behave correctly and incorrectly, but the new method in this paper derives only the latter. The new method also efficiently decides whether the derived condition is satisfied or not.

Original languageEnglish
Pages (from-to)38-44
Number of pages7
JournalSystems and Computers in Japan
Volume32
Issue number1
DOIs
Publication statusPublished - Jan 2001

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Combinatorial circuits
Logic circuits
Timing
Networks (circuits)
Output
Logic

ASJC Scopus subject areas

  • Hardware and Architecture
  • Information Systems
  • Theoretical Computer Science
  • Computational Theory and Mathematics

Cite this

Fast method for timing verification that uses the conditions that cause changes in the output values of gates. / Ohnishi, Atsushi; Sugiyama, Yuji.

In: Systems and Computers in Japan, Vol. 32, No. 1, 01.2001, p. 38-44.

Research output: Contribution to journalArticle

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