Fabrication method for IC-oriented Si twin-island single-electron transistors

Yukinori Ono, Yasuo Takahashi, Kenji Yamazaki, Masao Nagase, Hideo Namatsu, Kenji Kurihara, Katsumi Murase

Research output: Contribution to journalConference article

8 Citations (Scopus)

Abstract

A new fabrication method for Si single-electron transistors (SETs) is proposed. The method enables us to fabricate, in a self-aligned way, a twin-island SET in which two Si islands are aligned in parallel. Experimental devices demonstrated, at 40 K, that the twin-island SET structure can be operated as two individual SETs. Since the two SETs are packed in a tiny area, this method is suitable for constructing logic circuits based on pass-transistor-type logic and CMOS-type logic, which promises to lead to single-electron logic LSIs.

Original languageEnglish
Pages (from-to)123-126
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
Publication statusPublished - Dec 1 1998
EventProceedings of the 1998 IEEE International Electron Devices Meeting - San Francisco, CA, USA
Duration: Dec 6 1998Dec 9 1998

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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    Ono, Y., Takahashi, Y., Yamazaki, K., Nagase, M., Namatsu, H., Kurihara, K., & Murase, K. (1998). Fabrication method for IC-oriented Si twin-island single-electron transistors. Technical Digest - International Electron Devices Meeting, 123-126.