Fabrication method for IC-oriented Si single-electron transistors

Yukinori Ono, Yasuo Takahashi, Kenji Yamazaki, Masao Nagase, Hideo Namatsu, Kenji Kurihara, Katsumi Murase

Research output: Contribution to journalArticle

91 Citations (Scopus)

Abstract

A new fabrication method for Si single-electron transistors (SET's) is proposed. The method applies thermal oxidation to a Si wire with a fine trench across it on a silicon-on-insulator substrate. During the oxidation, the Si wire with the fine trench is converted, in a self-organized manner, into a twin SET structure with two single-electron islands, one along each edge of the trench, due to position-dependent oxidation-rate modulation caused by stress accumulation. Test devices demonstrated, at 40K, that the twin SET structure can operate as two individual SET's. Since the present method produces two SET's at the same time in a tiny area, it is suitable for integrating logic circuits based on pass-transistor-type logic and CMOS-type logic, which promises to lead to the fabrication of single-electron logic LSI's.

Original languageEnglish
Pages (from-to)147-153
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume47
Issue number1
DOIs
Publication statusPublished - Jan 1 2000

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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  • Cite this

    Ono, Y., Takahashi, Y., Yamazaki, K., Nagase, M., Namatsu, H., Kurihara, K., & Murase, K. (2000). Fabrication method for IC-oriented Si single-electron transistors. IEEE Transactions on Electron Devices, 47(1), 147-153. https://doi.org/10.1109/16.817580