Abstract
In this study, equivalent circuit modeling was examined to develop a method to evaluate cryptographic systems before fabrication. An equivalent circuit model of a cryptographic FPGA in which an advanced encryption standard (AES) algorithm had been implemented was determined from experimental measurements under the initial configuration of a power distribution network (PDN) of the FPGA. The model was implemented into a commercial analog circuit simulator, and power traces due to the simultaneous switching noise current were estimated under three different PDN configurations in which a decoupling circuit was inserted into the PDN as an on-board countermeasure. Estimated power traces were analyzed statistically by the correlation power analysis method to obtain correlation values, a major security index of AES. Variation of the correlation values with changes in decoupling configuration agreed with the corresponding experimental results. This means that the security of cryptographic devices against side-channel attacks can be evaluated by using the equivalent circuit model before fabrication.
| Original language | English |
|---|---|
| Article number | 6487397 |
| Pages (from-to) | 581-588 |
| Number of pages | 8 |
| Journal | IEEE Transactions on Electromagnetic Compatibility |
| Volume | 55 |
| Issue number | 3 |
| DOIs | |
| Publication status | Published - 2013 |
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Keywords
- Advanced encryption standard (AES)
- correlation power analysis (CPA)
- information leakage
- power distribution network (PDN)
- side-channel analysis
- simultaneous switching noise
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Condensed Matter Physics
- Atomic and Molecular Physics, and Optics
Cite this
Equivalent circuit modeling of cryptographic integrated circuit for information security design. / Iokibe, Kengo; Amano, Tetsuo; Okamoto, Kaoru; Toyota, Yoshitaka.
In: IEEE Transactions on Electromagnetic Compatibility, Vol. 55, No. 3, 6487397, 2013, p. 581-588.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Equivalent circuit modeling of cryptographic integrated circuit for information security design
AU - Iokibe, Kengo
AU - Amano, Tetsuo
AU - Okamoto, Kaoru
AU - Toyota, Yoshitaka
PY - 2013
Y1 - 2013
N2 - In this study, equivalent circuit modeling was examined to develop a method to evaluate cryptographic systems before fabrication. An equivalent circuit model of a cryptographic FPGA in which an advanced encryption standard (AES) algorithm had been implemented was determined from experimental measurements under the initial configuration of a power distribution network (PDN) of the FPGA. The model was implemented into a commercial analog circuit simulator, and power traces due to the simultaneous switching noise current were estimated under three different PDN configurations in which a decoupling circuit was inserted into the PDN as an on-board countermeasure. Estimated power traces were analyzed statistically by the correlation power analysis method to obtain correlation values, a major security index of AES. Variation of the correlation values with changes in decoupling configuration agreed with the corresponding experimental results. This means that the security of cryptographic devices against side-channel attacks can be evaluated by using the equivalent circuit model before fabrication.
AB - In this study, equivalent circuit modeling was examined to develop a method to evaluate cryptographic systems before fabrication. An equivalent circuit model of a cryptographic FPGA in which an advanced encryption standard (AES) algorithm had been implemented was determined from experimental measurements under the initial configuration of a power distribution network (PDN) of the FPGA. The model was implemented into a commercial analog circuit simulator, and power traces due to the simultaneous switching noise current were estimated under three different PDN configurations in which a decoupling circuit was inserted into the PDN as an on-board countermeasure. Estimated power traces were analyzed statistically by the correlation power analysis method to obtain correlation values, a major security index of AES. Variation of the correlation values with changes in decoupling configuration agreed with the corresponding experimental results. This means that the security of cryptographic devices against side-channel attacks can be evaluated by using the equivalent circuit model before fabrication.
KW - Advanced encryption standard (AES)
KW - correlation power analysis (CPA)
KW - information leakage
KW - power distribution network (PDN)
KW - side-channel analysis
KW - simultaneous switching noise
UR - http://www.scopus.com/inward/record.url?scp=84879422480&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84879422480&partnerID=8YFLogxK
U2 - 10.1109/TEMC.2013.2250505
DO - 10.1109/TEMC.2013.2250505
M3 - Article
AN - SCOPUS:84879422480
VL - 55
SP - 581
EP - 588
JO - IEEE Transactions on Electromagnetic Compatibility
JF - IEEE Transactions on Electromagnetic Compatibility
SN - 0018-9375
IS - 3
M1 - 6487397
ER -