Equivalent circuit modeling of cryptographic integrated circuit for information security design

Kengo Iokibe, Tetsuo Amano, Kaoru Okamoto, Yoshitaka Toyota

Research output: Contribution to journalArticle

8 Citations (Scopus)

Abstract

In this study, equivalent circuit modeling was examined to develop a method to evaluate cryptographic systems before fabrication. An equivalent circuit model of a cryptographic FPGA in which an advanced encryption standard (AES) algorithm had been implemented was determined from experimental measurements under the initial configuration of a power distribution network (PDN) of the FPGA. The model was implemented into a commercial analog circuit simulator, and power traces due to the simultaneous switching noise current were estimated under three different PDN configurations in which a decoupling circuit was inserted into the PDN as an on-board countermeasure. Estimated power traces were analyzed statistically by the correlation power analysis method to obtain correlation values, a major security index of AES. Variation of the correlation values with changes in decoupling configuration agreed with the corresponding experimental results. This means that the security of cryptographic devices against side-channel attacks can be evaluated by using the equivalent circuit model before fabrication.

Original languageEnglish
Article number6487397
Pages (from-to)581-588
Number of pages8
JournalIEEE Transactions on Electromagnetic Compatibility
Volume55
Issue number3
DOIs
Publication statusPublished - 2013

Fingerprint

Security of data
equivalent circuits
Electric power distribution
Equivalent circuits
integrated circuits
Integrated circuits
decoupling
Cryptography
Field programmable gate arrays (FPGA)
configurations
Fabrication
analog circuits
fabrication
countermeasures
Analog circuits
attack
simulators
Simulators
Networks (circuits)

Keywords

  • Advanced encryption standard (AES)
  • correlation power analysis (CPA)
  • information leakage
  • power distribution network (PDN)
  • side-channel analysis
  • simultaneous switching noise

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Condensed Matter Physics
  • Atomic and Molecular Physics, and Optics

Cite this

Equivalent circuit modeling of cryptographic integrated circuit for information security design. / Iokibe, Kengo; Amano, Tetsuo; Okamoto, Kaoru; Toyota, Yoshitaka.

In: IEEE Transactions on Electromagnetic Compatibility, Vol. 55, No. 3, 6487397, 2013, p. 581-588.

Research output: Contribution to journalArticle

@article{33a1f6a16d8e4b55b70786a4e7a1d303,
title = "Equivalent circuit modeling of cryptographic integrated circuit for information security design",
abstract = "In this study, equivalent circuit modeling was examined to develop a method to evaluate cryptographic systems before fabrication. An equivalent circuit model of a cryptographic FPGA in which an advanced encryption standard (AES) algorithm had been implemented was determined from experimental measurements under the initial configuration of a power distribution network (PDN) of the FPGA. The model was implemented into a commercial analog circuit simulator, and power traces due to the simultaneous switching noise current were estimated under three different PDN configurations in which a decoupling circuit was inserted into the PDN as an on-board countermeasure. Estimated power traces were analyzed statistically by the correlation power analysis method to obtain correlation values, a major security index of AES. Variation of the correlation values with changes in decoupling configuration agreed with the corresponding experimental results. This means that the security of cryptographic devices against side-channel attacks can be evaluated by using the equivalent circuit model before fabrication.",
keywords = "Advanced encryption standard (AES), correlation power analysis (CPA), information leakage, power distribution network (PDN), side-channel analysis, simultaneous switching noise",
author = "Kengo Iokibe and Tetsuo Amano and Kaoru Okamoto and Yoshitaka Toyota",
year = "2013",
doi = "10.1109/TEMC.2013.2250505",
language = "English",
volume = "55",
pages = "581--588",
journal = "IEEE Transactions on Electromagnetic Compatibility",
issn = "0018-9375",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "3",

}

TY - JOUR

T1 - Equivalent circuit modeling of cryptographic integrated circuit for information security design

AU - Iokibe, Kengo

AU - Amano, Tetsuo

AU - Okamoto, Kaoru

AU - Toyota, Yoshitaka

PY - 2013

Y1 - 2013

N2 - In this study, equivalent circuit modeling was examined to develop a method to evaluate cryptographic systems before fabrication. An equivalent circuit model of a cryptographic FPGA in which an advanced encryption standard (AES) algorithm had been implemented was determined from experimental measurements under the initial configuration of a power distribution network (PDN) of the FPGA. The model was implemented into a commercial analog circuit simulator, and power traces due to the simultaneous switching noise current were estimated under three different PDN configurations in which a decoupling circuit was inserted into the PDN as an on-board countermeasure. Estimated power traces were analyzed statistically by the correlation power analysis method to obtain correlation values, a major security index of AES. Variation of the correlation values with changes in decoupling configuration agreed with the corresponding experimental results. This means that the security of cryptographic devices against side-channel attacks can be evaluated by using the equivalent circuit model before fabrication.

AB - In this study, equivalent circuit modeling was examined to develop a method to evaluate cryptographic systems before fabrication. An equivalent circuit model of a cryptographic FPGA in which an advanced encryption standard (AES) algorithm had been implemented was determined from experimental measurements under the initial configuration of a power distribution network (PDN) of the FPGA. The model was implemented into a commercial analog circuit simulator, and power traces due to the simultaneous switching noise current were estimated under three different PDN configurations in which a decoupling circuit was inserted into the PDN as an on-board countermeasure. Estimated power traces were analyzed statistically by the correlation power analysis method to obtain correlation values, a major security index of AES. Variation of the correlation values with changes in decoupling configuration agreed with the corresponding experimental results. This means that the security of cryptographic devices against side-channel attacks can be evaluated by using the equivalent circuit model before fabrication.

KW - Advanced encryption standard (AES)

KW - correlation power analysis (CPA)

KW - information leakage

KW - power distribution network (PDN)

KW - side-channel analysis

KW - simultaneous switching noise

UR - http://www.scopus.com/inward/record.url?scp=84879422480&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84879422480&partnerID=8YFLogxK

U2 - 10.1109/TEMC.2013.2250505

DO - 10.1109/TEMC.2013.2250505

M3 - Article

VL - 55

SP - 581

EP - 588

JO - IEEE Transactions on Electromagnetic Compatibility

JF - IEEE Transactions on Electromagnetic Compatibility

SN - 0018-9375

IS - 3

M1 - 6487397

ER -