Dynamically reconfigurable vision-chip architecture

Maki Yasuda, Minoru Watanabe

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

Recently, for autonomous vehicles and robots, demand has been increasing for high-speed image recognition that is superior to that of the human eye. To date, analogtype vision chips and digital vision chips have been developed. Nevertheless, even now, to realize such high-speed real-time image recognition operation is extremely difficult. Therefore, to realize a high-speed real-time image-recognizable vision chip, this paper presents a proposal for a dynamically reconfigurable vision chip architecture. In addition, some experimental results are reported.

Original languageEnglish
Title of host publicationProceedings - 2010 International Conference on Field Programmable Logic and Applications, FPL 2010
Pages508-512
Number of pages5
DOIs
Publication statusPublished - 2010
Externally publishedYes
Event20th International Conference on Field Programmable Logic and Applications, FPL 2010 - Milano, Italy
Duration: Aug 31 2010Sep 2 2010

Publication series

NameProceedings - 2010 International Conference on Field Programmable Logic and Applications, FPL 2010

Conference

Conference20th International Conference on Field Programmable Logic and Applications, FPL 2010
Country/TerritoryItaly
CityMilano
Period8/31/109/2/10

Keywords

  • Dynamically reconfigurable devices
  • Field programmable gate arrays
  • Vision chips

ASJC Scopus subject areas

  • Computer Science Applications
  • Hardware and Architecture

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