Dynamically reconfigurable logic LSI: PCA-2

Hideyuki Ito, Ryusuke Konishi, Hiroshi Nakada, Hideyuki Tsuboi, Yuichi Okuyama, Akira Nagoya

Research output: Contribution to journalArticle

8 Citations (Scopus)

Abstract

Design points and the results seen in the development of a dynamically reconfigurable logic LSI, PCA-2, are described. PCA-2 enables the realization of flexible parallel processing based on the autonomous reconfiguration of logic circuits. To realize this feature, we introduce an asynchronous circuit design and a homogeneous cell array structure. PCA-2 represents an advance on the earlier LSI, PCA-1. Cutting edge CMOS technology is used to realize the structural merits of PCA hardware. Compared to PCA-1, PCA-2 offers 16 times greater integration level for programmable logic. Due to miniaturization and design refinement, PCA-2 provides a 6-fold increase in the circuit frequency of the configuration controller and a 3-fold increase in the operating frequency of the programmable logic. The results gained confirm the effects of refinement and the suitability of our architecture for device miniaturization.

Original languageEnglish
Pages (from-to)2011-2020
Number of pages10
JournalIEICE Transactions on Information and Systems
VolumeE87-D
Issue number8
Publication statusPublished - Aug 2004
Externally publishedYes

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Networks (circuits)
Logic circuits
Hardware
Controllers
Processing

Keywords

  • Asynchronous circuit
  • Autonomous reconfiguration
  • Dynamically reconfigurable hardware
  • Parallel computing

ASJC Scopus subject areas

  • Information Systems
  • Computer Graphics and Computer-Aided Design
  • Software

Cite this

Ito, H., Konishi, R., Nakada, H., Tsuboi, H., Okuyama, Y., & Nagoya, A. (2004). Dynamically reconfigurable logic LSI: PCA-2. IEICE Transactions on Information and Systems, E87-D(8), 2011-2020.

Dynamically reconfigurable logic LSI : PCA-2. / Ito, Hideyuki; Konishi, Ryusuke; Nakada, Hiroshi; Tsuboi, Hideyuki; Okuyama, Yuichi; Nagoya, Akira.

In: IEICE Transactions on Information and Systems, Vol. E87-D, No. 8, 08.2004, p. 2011-2020.

Research output: Contribution to journalArticle

Ito, H, Konishi, R, Nakada, H, Tsuboi, H, Okuyama, Y & Nagoya, A 2004, 'Dynamically reconfigurable logic LSI: PCA-2', IEICE Transactions on Information and Systems, vol. E87-D, no. 8, pp. 2011-2020.
Ito H, Konishi R, Nakada H, Tsuboi H, Okuyama Y, Nagoya A. Dynamically reconfigurable logic LSI: PCA-2. IEICE Transactions on Information and Systems. 2004 Aug;E87-D(8):2011-2020.
Ito, Hideyuki ; Konishi, Ryusuke ; Nakada, Hiroshi ; Tsuboi, Hideyuki ; Okuyama, Yuichi ; Nagoya, Akira. / Dynamically reconfigurable logic LSI : PCA-2. In: IEICE Transactions on Information and Systems. 2004 ; Vol. E87-D, No. 8. pp. 2011-2020.
@article{bead401f84b149ae95dd2b3574bf682e,
title = "Dynamically reconfigurable logic LSI: PCA-2",
abstract = "Design points and the results seen in the development of a dynamically reconfigurable logic LSI, PCA-2, are described. PCA-2 enables the realization of flexible parallel processing based on the autonomous reconfiguration of logic circuits. To realize this feature, we introduce an asynchronous circuit design and a homogeneous cell array structure. PCA-2 represents an advance on the earlier LSI, PCA-1. Cutting edge CMOS technology is used to realize the structural merits of PCA hardware. Compared to PCA-1, PCA-2 offers 16 times greater integration level for programmable logic. Due to miniaturization and design refinement, PCA-2 provides a 6-fold increase in the circuit frequency of the configuration controller and a 3-fold increase in the operating frequency of the programmable logic. The results gained confirm the effects of refinement and the suitability of our architecture for device miniaturization.",
keywords = "Asynchronous circuit, Autonomous reconfiguration, Dynamically reconfigurable hardware, Parallel computing",
author = "Hideyuki Ito and Ryusuke Konishi and Hiroshi Nakada and Hideyuki Tsuboi and Yuichi Okuyama and Akira Nagoya",
year = "2004",
month = "8",
language = "English",
volume = "E87-D",
pages = "2011--2020",
journal = "IEICE Transactions on Information and Systems",
issn = "0916-8532",
publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
number = "8",

}

TY - JOUR

T1 - Dynamically reconfigurable logic LSI

T2 - PCA-2

AU - Ito, Hideyuki

AU - Konishi, Ryusuke

AU - Nakada, Hiroshi

AU - Tsuboi, Hideyuki

AU - Okuyama, Yuichi

AU - Nagoya, Akira

PY - 2004/8

Y1 - 2004/8

N2 - Design points and the results seen in the development of a dynamically reconfigurable logic LSI, PCA-2, are described. PCA-2 enables the realization of flexible parallel processing based on the autonomous reconfiguration of logic circuits. To realize this feature, we introduce an asynchronous circuit design and a homogeneous cell array structure. PCA-2 represents an advance on the earlier LSI, PCA-1. Cutting edge CMOS technology is used to realize the structural merits of PCA hardware. Compared to PCA-1, PCA-2 offers 16 times greater integration level for programmable logic. Due to miniaturization and design refinement, PCA-2 provides a 6-fold increase in the circuit frequency of the configuration controller and a 3-fold increase in the operating frequency of the programmable logic. The results gained confirm the effects of refinement and the suitability of our architecture for device miniaturization.

AB - Design points and the results seen in the development of a dynamically reconfigurable logic LSI, PCA-2, are described. PCA-2 enables the realization of flexible parallel processing based on the autonomous reconfiguration of logic circuits. To realize this feature, we introduce an asynchronous circuit design and a homogeneous cell array structure. PCA-2 represents an advance on the earlier LSI, PCA-1. Cutting edge CMOS technology is used to realize the structural merits of PCA hardware. Compared to PCA-1, PCA-2 offers 16 times greater integration level for programmable logic. Due to miniaturization and design refinement, PCA-2 provides a 6-fold increase in the circuit frequency of the configuration controller and a 3-fold increase in the operating frequency of the programmable logic. The results gained confirm the effects of refinement and the suitability of our architecture for device miniaturization.

KW - Asynchronous circuit

KW - Autonomous reconfiguration

KW - Dynamically reconfigurable hardware

KW - Parallel computing

UR - http://www.scopus.com/inward/record.url?scp=4344602993&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=4344602993&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:4344602993

VL - E87-D

SP - 2011

EP - 2020

JO - IEICE Transactions on Information and Systems

JF - IEICE Transactions on Information and Systems

SN - 0916-8532

IS - 8

ER -