Abstract
This paper describes the realization of a dynamically reconfigurable logic LSI based on a novel parallel computer architecture. The key point of the architecture is its dual-structured cell array which enables dynamic and autonomous reconfiguration of the logic circuits. The LSI was completed by successfully introducing two specific features: fully asynchronous logic circuits and a homogeneous structure, only LUTs are used.
Original language | English |
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Pages (from-to) | 859-867 |
Number of pages | 9 |
Journal | IEICE Transactions on Information and Systems |
Volume | E86-D |
Issue number | 5 |
Publication status | Published - May 2003 |
Externally published | Yes |
Keywords
- Asynchronous circuit design
- Autonomous reconfigurability
- Reconfigurable computing
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Computer Vision and Pattern Recognition
- Electrical and Electronic Engineering
- Artificial Intelligence