Dynamically reconfigurable logic LSI - PCA-1

H. Ito; R. Konishi; H. Nakada; K. Oguri; A. Nagoya; N. Imlig; K. Nagami; T. Shiozawa; M. Inamori

Dynamically reconfigurable logic LSI - PCA-1

H. Ito, R. Konishi, H. Nakada, K. Oguri, A. Nagoya, N. Imlig, K. Nagami, T. Shiozawa, M. Inamori

Research output: Contribution to conference › Paper › peer-review

Abstract

This paper describes the realization of a dynamically reconfigurable logic LSI based on a novel parallel computer architecture. The key point of the architecture is its dual-structured cell array to enable dynamic and autonomous reconfiguration of the logic circuit. The LSI was completed with successfully introducing two specific features: fully asynchronous logic circuits and homogeneous structure using only LUTs.

Original language	English
Pages	103-106
Number of pages	4
Publication status	Published - Jan 1 2001
Externally published	Yes
Event	2001 VLSI Circuits Symposium - Kyoto, Japan Duration: Jun 14 2001 → Jun 16 2001

Other

Other	2001 VLSI Circuits Symposium
Country/Territory	Japan
City	Kyoto
Period	6/14/01 → 6/16/01

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

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abstract = "This paper describes the realization of a dynamically reconfigurable logic LSI based on a novel parallel computer architecture. The key point of the architecture is its dual-structured cell array to enable dynamic and autonomous reconfiguration of the logic circuit. The LSI was completed with successfully introducing two specific features: fully asynchronous logic circuits and homogeneous structure using only LUTs.",

author = "H. Ito and R. Konishi and H. Nakada and K. Oguri and A. Nagoya and N. Imlig and K. Nagami and T. Shiozawa and M. Inamori",

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AU - Ito, H.

AU - Konishi, R.

AU - Nakada, H.

AU - Oguri, K.

AU - Nagoya, A.

AU - Imlig, N.

AU - Nagami, K.

AU - Shiozawa, T.

AU - Inamori, M.

PY - 2001/1/1

Y1 - 2001/1/1

N2 - This paper describes the realization of a dynamically reconfigurable logic LSI based on a novel parallel computer architecture. The key point of the architecture is its dual-structured cell array to enable dynamic and autonomous reconfiguration of the logic circuit. The LSI was completed with successfully introducing two specific features: fully asynchronous logic circuits and homogeneous structure using only LUTs.

AB - This paper describes the realization of a dynamically reconfigurable logic LSI based on a novel parallel computer architecture. The key point of the architecture is its dual-structured cell array to enable dynamic and autonomous reconfiguration of the logic circuit. The LSI was completed with successfully introducing two specific features: fully asynchronous logic circuits and homogeneous structure using only LUTs.

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M3 - Paper

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T2 - 2001 VLSI Circuits Symposium

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ER -

Dynamically reconfigurable logic LSI - PCA-1

Abstract

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ASJC Scopus subject areas

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