We present a proposal of a partial reconfiguration architecture for optically reconfigurable gate arrays and present an 11,424 gate dynamic optically reconfigurable gate array VLSI chip that was fabricated on a 96:04 mm2 chip using an 0:35 μm three-metal complementary metal oxide semiconductor process technology. The fabricated VLSI chip achieved a 2:21 μs partial reconfiguration.
ASJC Scopus subject areas
- Atomic and Molecular Physics, and Optics
- Engineering (miscellaneous)
- Electrical and Electronic Engineering