Dynamic optically reconfigurable gate array very large-scale integration with partial reconfiguration capability

Daisaku Seto, Mao Nakajima, Minoru Watanabe

Research output: Contribution to journalArticlepeer-review

23 Citations (Scopus)

Abstract

We present a proposal of a partial reconfiguration architecture for optically reconfigurable gate arrays and present an 11,424 gate dynamic optically reconfigurable gate array VLSI chip that was fabricated on a 96:04 mm2 chip using an 0:35 μm three-metal complementary metal oxide semiconductor process technology. The fabricated VLSI chip achieved a 2:21 μs partial reconfiguration.

Original languageEnglish
Pages (from-to)6986-6994
Number of pages9
JournalApplied Optics
Volume49
Issue number36
DOIs
Publication statusPublished - Dec 20 2010
Externally publishedYes

ASJC Scopus subject areas

  • Atomic and Molecular Physics, and Optics
  • Engineering (miscellaneous)
  • Electrical and Electronic Engineering

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