Inverters using SiC or GaN power devices can realize high frequency and high efficiency operation. To achieve high efficiency, the switching characteristics of these power devices are important, because stray inductances in inverter main circuit have strong influence on the switching characteristics. To reduce the switching loss and surge voltage, minimization of stray inductance in the main circuit is required for high-frequency PWM inverter. This paper describes design guidelines for high-frequency inverters that realize low inductance. The PCB design guideline on the thick multilayer PCB is derived from the inductance calculation using 3D-FEA. It is shown experimentally, that the stray inductance of designed PCB can be reduced to the same level as the inductance inside the power devices. Experimental results verify that a prototype can achieve high speed switching and can suppress surge voltage. A load test is demonstrated to evaluate main circuit efficiency in half-bridge inverter at 100 kHz.