Development of a CMOS SOI pixel detector

Y. Arai; M. Hazumi; Y. Ikegami; T. Kohriki; O. Tajima; S. Terada; T. Tsuboyama; Y. Unno; Y. Ushiroda; H. Ikeda; K. Hara; H. Ishino; T. Kawasaki; H. Miyake; E. Martin; G. Varner; H. Tajima; M. Ohno; K. Fukuda; H. Komatsubara; J. Ida

Development of a CMOS SOI pixel detector

Y. Arai, M. Hazumi, Y. Ikegami, T. Kohriki, O. Tajima, S. Terada, T. Tsuboyama, Y. Unno, Y. Ushiroda, H. Ikeda, K. Hara, H. Ishino, T. Kawasaki, H. Miyake, E. Martin, G. Varner, H. Tajima, M. Ohno, K. Fukuda, H. KomatsubaraJ. Ida

Research output: Contribution to conference › Paper › peer-review

2 Citations (Scopus)

Abstract

We have developed a monolithic radiation pixel detector using silicon on insulator (SOI) with a commercial 0.15 μm fullydepleted-SOI technology and a Czochralski high resistivity silicon substrate in place of a handle wafer. The SOI TEG (Test Element Group) chips with a size of 2.5 × 2.5 mm² consisting of 20 × 20 μ m² pixels have been designed and manufactured. Performance tests with a laser light illumination and a β ray radioactive source indicate successful operation of the detector. We also briefly discuss the back gate effect as well as the simulation study.

Original language	English
Pages	263-266
Number of pages	4
Publication status	Published - 2007
Externally published	Yes
Event	12th Workshop on Electronics for LHC and Future Experiments, LECC 2006 - Valencia, Spain Duration: Sept 25 2006 → Sept 29 2006

Other

Other	12th Workshop on Electronics for LHC and Future Experiments, LECC 2006
Country/Territory	Spain
City	Valencia
Period	9/25/06 → 9/29/06

ASJC Scopus subject areas

Nuclear and High Energy Physics

Cite this

Arai, Y., Hazumi, M., Ikegami, Y., Kohriki, T., Tajima, O., Terada, S., Tsuboyama, T., Unno, Y., Ushiroda, Y., Ikeda, H., Hara, K., Ishino, H., Kawasaki, T., Miyake, H., Martin, E., Varner, G., Tajima, H., Ohno, M., Fukuda, K., ... Ida, J. (2007). Development of a CMOS SOI pixel detector. 263-266. Paper presented at 12th Workshop on Electronics for LHC and Future Experiments, LECC 2006, Valencia, Spain.

Arai, Y, Hazumi, M, Ikegami, Y, Kohriki, T, Tajima, O, Terada, S, Tsuboyama, T, Unno, Y, Ushiroda, Y, Ikeda, H, Hara, K, Ishino, H, Kawasaki, T, Miyake, H, Martin, E, Varner, G, Tajima, H, Ohno, M, Fukuda, K, Komatsubara, H & Ida, J 2007, 'Development of a CMOS SOI pixel detector', Paper presented at 12th Workshop on Electronics for LHC and Future Experiments, LECC 2006, Valencia, Spain, 9/25/06 - 9/29/06 pp. 263-266.

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author = "Y. Arai and M. Hazumi and Y. Ikegami and T. Kohriki and O. Tajima and S. Terada and T. Tsuboyama and Y. Unno and Y. Ushiroda and H. Ikeda and K. Hara and H. Ishino and T. Kawasaki and H. Miyake and E. Martin and G. Varner and H. Tajima and M. Ohno and K. Fukuda and H. Komatsubara and J. Ida",

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pages = "263--266",

note = "12th Workshop on Electronics for LHC and Future Experiments, LECC 2006 ; Conference date: 25-09-2006 Through 29-09-2006",

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TY - CONF

T1 - Development of a CMOS SOI pixel detector

AU - Arai, Y.

AU - Hazumi, M.

AU - Ikegami, Y.

AU - Kohriki, T.

AU - Tajima, O.

AU - Terada, S.

AU - Tsuboyama, T.

AU - Unno, Y.

AU - Ushiroda, Y.

AU - Ikeda, H.

AU - Hara, K.

AU - Ishino, H.

AU - Kawasaki, T.

AU - Miyake, H.

AU - Martin, E.

AU - Varner, G.

AU - Tajima, H.

AU - Ohno, M.

AU - Fukuda, K.

AU - Komatsubara, H.

AU - Ida, J.

PY - 2007

Y1 - 2007

N2 - We have developed a monolithic radiation pixel detector using silicon on insulator (SOI) with a commercial 0.15 μm fullydepleted-SOI technology and a Czochralski high resistivity silicon substrate in place of a handle wafer. The SOI TEG (Test Element Group) chips with a size of 2.5 × 2.5 mm2 consisting of 20 × 20 μ m2 pixels have been designed and manufactured. Performance tests with a laser light illumination and a β ray radioactive source indicate successful operation of the detector. We also briefly discuss the back gate effect as well as the simulation study.

AB - We have developed a monolithic radiation pixel detector using silicon on insulator (SOI) with a commercial 0.15 μm fullydepleted-SOI technology and a Czochralski high resistivity silicon substrate in place of a handle wafer. The SOI TEG (Test Element Group) chips with a size of 2.5 × 2.5 mm2 consisting of 20 × 20 μ m2 pixels have been designed and manufactured. Performance tests with a laser light illumination and a β ray radioactive source indicate successful operation of the detector. We also briefly discuss the back gate effect as well as the simulation study.

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T2 - 12th Workshop on Electronics for LHC and Future Experiments, LECC 2006

Y2 - 25 September 2006 through 29 September 2006

ER -

Development of a CMOS SOI pixel detector

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ASJC Scopus subject areas

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