TY - GEN
T1 - Design of a parallel-operation-oriented FPGA
AU - Watanabe, Minoru
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/6/23
Y1 - 2015/6/23
N2 - Recently, studies of acceleration of software operations on a processor have been executed aggressively using Field Programmable Gate Arrays (FPGAs). However, currently available FPGA architecture presents waste under a parallel operation in terms of configuration memory because the same configuration context corresponding to same-function modules must be programmed onto numerous parts of configuration memory. This paper therefore presents a proposal for a parallel-operation-oriented FPGA architecture including a shared common configuration memory. In this research, a parallel-operation-oriented FPGA with four programmable gate arrays sharing a common configuration memory has been designed using a 0.18 μm CMOS process technology. The advantage of the parallel-operation-oriented FPGA is clarified and a design technique to achieve a high-performance parallel-operation-oriented FPGA is discussed.
AB - Recently, studies of acceleration of software operations on a processor have been executed aggressively using Field Programmable Gate Arrays (FPGAs). However, currently available FPGA architecture presents waste under a parallel operation in terms of configuration memory because the same configuration context corresponding to same-function modules must be programmed onto numerous parts of configuration memory. This paper therefore presents a proposal for a parallel-operation-oriented FPGA architecture including a shared common configuration memory. In this research, a parallel-operation-oriented FPGA with four programmable gate arrays sharing a common configuration memory has been designed using a 0.18 μm CMOS process technology. The advantage of the parallel-operation-oriented FPGA is clarified and a design technique to achieve a high-performance parallel-operation-oriented FPGA is discussed.
UR - http://www.scopus.com/inward/record.url?scp=84939438946&partnerID=8YFLogxK
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U2 - 10.1109/ISNE.2015.7132021
DO - 10.1109/ISNE.2015.7132021
M3 - Conference contribution
AN - SCOPUS:84939438946
T3 - 4th International Symposium on Next-Generation Electronics, IEEE ISNE 2015
BT - 4th International Symposium on Next-Generation Electronics, IEEE ISNE 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 4th International Symposium on Next-Generation Electronics, IEEE ISNE 2015
Y2 - 4 May 2015 through 6 May 2015
ER -