Design of a parallel-operation-oriented FPGA

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

Recently, studies of acceleration of software operations on a processor have been executed aggressively using Field Programmable Gate Arrays (FPGAs). However, currently available FPGA architecture presents waste under a parallel operation in terms of configuration memory because the same configuration context corresponding to same-function modules must be programmed onto numerous parts of configuration memory. This paper therefore presents a proposal for a parallel-operation-oriented FPGA architecture including a shared common configuration memory. In this research, a parallel-operation-oriented FPGA with four programmable gate arrays sharing a common configuration memory has been designed using a 0.18 μm CMOS process technology. The advantage of the parallel-operation-oriented FPGA is clarified and a design technique to achieve a high-performance parallel-operation-oriented FPGA is discussed.

Original languageEnglish
Title of host publication4th International Symposium on Next-Generation Electronics, IEEE ISNE 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479942084
DOIs
Publication statusPublished - Jun 23 2015
Externally publishedYes
Event4th International Symposium on Next-Generation Electronics, IEEE ISNE 2015 - Taipei, Taiwan, Province of China
Duration: May 4 2015May 6 2015

Publication series

Name4th International Symposium on Next-Generation Electronics, IEEE ISNE 2015

Conference

Conference4th International Symposium on Next-Generation Electronics, IEEE ISNE 2015
Country/TerritoryTaiwan, Province of China
CityTaipei
Period5/4/155/6/15

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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